5 Error Signaling Module Overview

The Error Signaling Module (ESM) provides systematic consolidation of responses to error events throughout the device into one location which is crucial for several safety critical applications.

ESM Subsystem contains following modules:

1. ESM CPU1 - Dedicated ESM module for output to CPU1
2. ESM CPU2 - Dedicated ESM module for output to CPU2
3. ESM CPU3 - Dedicated ESM module for output to CPU3
4. System ESM - Dedicated ESM module for system level outputs (mainly the ERRORSTS pin output, device reset, and integration to other modules using XBAR event outputs)

Figure 5-1 describes how the ESM subsystem integrates at the device level in detail, for more info refer to ESM chapter in the F29x TRM.

Figure 5-1 ESM Subsystem Integration Block Diagram

The ESM provides features to classify errors by severity and to provide programmable error response. Error Signaling Module provides a way to indicate error pin response, selectable interrupt priority response, or Non-Maskable interrupt (NMI) to CPU depending on severity of error encountered. The user is responsible to determine what error response is to be taken for each error event so that this is consistent with the system safety concept.

1. Interrupt to specific CPU:
   1. Interrupt (INT or RTINT from PIPE to CPU) (Low priority interrupt output of ESM) - Generally selected for correctable or low severity errors encountered in the device or can be implemented for diagnostics outside the CPU. An interrupt allows events external to the CPU to generate a program sequence context transfer to an interrupt handler where software has an opportunity to manage the fault.
   2. Non-Maskable Interrupt (NMI) (High priority interrupt output of ESM) - Generally selected for uncorrectable or critical errors encountered in the device where error response is required to transfer context to NMI ISR and software has an opportunity to manage the fault and abort the operation safely.
2. Error Signaling Pin:
   1. Error pin (ERRORSTS) action for external monitor like PMIC (Power management integrated circuits) to act for cases where required response is to generate an external error response.
3. Resets
   1. Respective CPU Reset (CPURSn): ESM is capable of generating reset to individual CPU to bring system in safe state upon detection of error in MCU.
   2. Device Reset (XRSn): Upon detection of error, trigger device reset (XRSn) to bring MCU in safe state.

The section below gives a brief overview of configurations for the ESM CPU and System ESM modules for above outputs in ESM subsystem for more details refer to the ESM chapter in F29x Technical Reference Manual and device integration.

Overview and key points to know about error events in ESM:

1. Error events are common to all ESM module (ESM CPU1/2/3 and System ESM)
2. Each ESM module has separate configuration and status registers hence all ESM modules can work independently of each other allowing flexibility for different use cases. For example, an error event on the occurrence can be configured to output an interrupt to CPU1 from ESM CPU1 and not configured to output an interrupt to CPU3 from ESM CPU3 module.
3. Error events are divided in further groups of 32. F29x devices have total of 256 error events hence there are total 8 Groups.