SDAA104 September   2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Error Handling Architecture Overview
  6. 3Example Overview
  7. 4Error Aggregator Overview
    1. 4.1 Error Aggregation
    2. 4.2 Error Logging
    3. 4.3 Error Debugging Using EAM Module
      1. 4.3.1 EAM Error Debugging
      2. 4.3.2 Interpreting Error Address and Program Counter Values
  8. 5Error Signaling Module Overview
    1. 5.1 ESM Error Event Output Configuration and Status Information
      1. 5.1.1 Sysconfig ESM Configuration
    2. 5.2 ESM Error Events Debugging
    3. 5.3 Miscellaneous Debug Tips for ESM
  9. 6BootROM EAM and ESM Error Status
  10. 7FAQ's:
  11. 8Summary
  12. 9References

4.3.2 Interpreting Error Address and Program Counter Values

As explained in section 3.2, error address and program counter addresses can be used for debugging source of the error. This section showcases interpretation of error address and program counter taking esm multicore example (esm_ex1_cpu1_cpu3) from the F29 SDK.

The program counter (PC) address can be copied to the CCS disassembly view to find the source code where the error occurred. For this example, when looking at the corresponding PC address CCS disassembly view for the EAM captured PC address (0x10402C14) as shown in Figure 4-7, points to the data write operation to location 0x20000000 (M0 RAM) also logged in the High Priority Address register in EAM. Hence with the PC address and error address information, user can pin-point the issue to a specific CPU3 source code write operation to memory location that caused the error.

The error occurred on CPU3 DW (data write) bus which also matches the expected behavior from the code perspective since the CPU3 application code has write operation for the M0RAM_data to M0RAM which is not allowed from CPU3 code. CPU3 only has read data permission for M0RAM hence write operation in this case caused security violation error on CPU3 DW bus.

Disassembly View of Program Counter Figure 4-7 Disassembly View of Program Counter
Table 4-2 M0RAM Access from CPU3
Memory Interleaved CPU1 CPU2 CPU3 HSM RTDMA1 RTDMA2
M0 RAM Yes 0WS data (read and write) 0WS data (read-only) 3WS data (read-only) - - -