SDAA104 September   2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Error Handling Architecture Overview
  6. 3Example Overview
  7. 4Error Aggregator Overview
    1. 4.1 Error Aggregation
    2. 4.2 Error Logging
    3. 4.3 Error Debugging Using EAM Module
      1. 4.3.1 EAM Error Debugging
      2. 4.3.2 Interpreting Error Address and Program Counter Values
  8. 5Error Signaling Module Overview
    1. 5.1 ESM Error Event Output Configuration and Status Information
      1. 5.1.1 Sysconfig ESM Configuration
    2. 5.2 ESM Error Events Debugging
    3. 5.3 Miscellaneous Debug Tips for ESM
  9. 6BootROM EAM and ESM Error Status
  10. 7FAQ's:
  11. 8Summary
  12. 9References

5.2 ESM Error Events Debugging

Follow the below steps for error events debug :

  1. Run the following scripts ESM_CPU_Check_Status() GEL file hot menu function from CCS to check status of the error events as shown in Figure 5-6. This function output indicates error events separated in two categories:
    1. Active/Pending Error Events – Indicates error events that are active/pending
      1. When an error event is active means the raw status of the error event is set, the function checks for RAW status register (RAW_j) for each event stated in F29x TRM ESM error events table.
    2. Active, Pending, and Enabled Error Events – Indicates error events that are active/pending and enabled.
      1. When an error event is active, pending and enabled means that the RAW status is set for the error event as well as the Interrupt Enable Set Register is also set by the user to trigger interrupt output from respective ESM module.
        ESM Error Status GEL Function Figure 5-6 ESM Error Status GEL Function
  2. Example output from the GEL output and correlation to the ESM registers is shown in the figure below. This is continuation of the same ESM Multicore example taken from F29 SDK.
    1. Figure 5-7 shows the CPU1_ERAD_NMI error event is both active and enabled. The ESM CPU1 - Interrupt priority register (INT_PRIO) is also set for the CPU1_ERAD_NMI error event to trigger NMI both for CPU1 (in ESM CPU1) and CPU3 (in ESM CPU3).
    2. In addition to this there are other error events like ErrorAggregator_CPU3_HPERR (Error aggregator CPU3 high priority error from security violation error on CPU3 DW bus as explained in sections above), EPWMXBAR1, CPU1 High Priority interrupt and CPU3 High priority interrupt output also active which is decoded using the ESM RAW Status register (RAW_j) value. CPU1 and CPU3 high priority interrupt outputs are CPU1 and CPU3 NMI output flags whereas EPWM XBAR and ERAD NMI events are used in the NMI errata workaround implementation hence active as expected, check details in the F29x device errata.
      ESM Error Event Status GEL Output Figure 5-7 ESM Error Event Status GEL Output
  3. Similar to EAM register flags, check for the GEL output before RAW status register is cleared in NMI ISR or check the same structure (nmiStatus) as shown before where they are saved for debug later. Clearing ESM RAW status (RAW_j) register flags is necessary to avoid the NMIWD timeout in case particular event is configured to trigger NMI when active.