SDAA516 August   2026 AM620-Q1 , AM623 , AM625-Q1 , AM62A1-Q1 , AM62A3-Q1 , AM62A7-Q1 , AM62D-Q1 , AM62L , AM62P-Q1 , DRA821U-Q1 , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Purpose
    2. 1.2 Scope
  5. 2Detailed Description
    1. 2.1 AM62Ax QSPI Boot Overview
      1. 2.1.1 Boot Preconditions
      2. 2.1.2 Boot ROM Read Sequence
    2. 2.2 Flash Addressing Architecture
      1. 2.2.1 3-Byte Addressing Mode
      2. 2.2.2 4-Byte Addressing Mode
      3. 2.2.3 State Retention Behavior
    3. 2.3 Boot Compatibility Considerations
      1. 2.3.1 Boot ROM Expectations
      2. 2.3.2 Addressing-Mode Mismatch Mechanism
      3. 2.3.3 Start-Up Impact
    4. 2.4 Example Start-Up Investigation
      1. 2.4.1 External Failure Symptoms
      2. 2.4.2 Boot ROM Log Analysis
      3. 2.4.3 Memory Verification Using CCS
      4. 2.4.4 Image Comparison
      5. 2.4.5 QSPI Bus Analysis
      6. 2.4.6 Root Cause Confirmation
    5. 2.5 Debug Methodology
    6. 2.6 Mitigation and Design Recommendations
      1. 2.6.1 Preferred Solution: Flash Reset Synchronization
      2. 2.6.2 Alternative Solution: Driver-Level Mitigation
      3. 2.6.3 Applicability of the 0x6C Mitigation
      4. 2.6.4 Design Constraints for Large-Capacity Flash Applications
  6. 3Summary
  7. 4References

2.3.1 Boot ROM Expectations

During start-up, the AM62Ax Boot ROM always assumes that the Flash device is operating in 3-byte addressing mode.

The Boot ROM issues command 0x6B followed by a fixed 3-byte address phase and eight dummy cycles. The Boot ROM does not provide any mechanism to detect the current addressing mode of the Flash device.