SLAA649G October   2014  – August 2021 MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2013-EP , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2254 , MSP430F2272 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F249-EP , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430F2619S-HT , MSP430FR2032 , MSP430FR2033 , MSP430FR2110 , MSP430FR2111 , MSP430FR2153 , MSP430FR2155 , MSP430FR2310 , MSP430FR2311 , MSP430FR2353 , MSP430FR2355 , MSP430FR2433 , MSP430FR2475 , MSP430FR2476 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2230-EP , MSP430G2231 , MSP430G2231-EP , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2302-EP , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2332-EP , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430I2020 , MSP430I2021 , MSP430I2030 , MSP430I2031 , MSP430I2040 , MSP430I2041

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Comparison of MSP430FR4xx and MSP430FR2xx Devices
  4. 3 In-System Programming of Nonvolatile Memory
    1. 3.1 Ferroelectric RAM (FRAM) Overview
    2. 3.2 FRAM Cell
    3. 3.3 Protecting FRAM Using the Memory Write Protection Bit
    4. 3.4 FRAM Memory Wait States
    5. 3.5 Bootloader (BSL)
    6. 3.6 JTAG and Security
    7. 3.7 Production Programming
  5. 4 Hardware Migration Considerations
  6. 5 Device Calibration Information
  7. 6 Important Device Specifications
  8. 7 Core Architecture Considerations
    1. 7.1 Power Management Module (PMM)
      1. 7.1.1 Core LDO and LPM3.5 LDO
      2. 7.1.2 SVS
      3. 7.1.3 VREF
      4. 7.1.4 Debug in Low-Power Mode
    2. 7.2 Clock System
      1. 7.2.1 DCO Frequencies
      2. 7.2.2 FLL, REFO, and DCO Tap
      3. 7.2.3 FRAM Access at 16 MHz, ADC Clock, and Clocks-on-Demand
    3. 7.3 Operating Modes, Wake-up Times, and Reset
      1. 7.3.1 LPMx.5
      2. 7.3.2 Reset
        1. 7.3.2.1 Behavior of POR and BOR
        2. 7.3.2.2 Reset Generation
        3. 7.3.2.3 Determining the Cause of Reset
    4. 7.4 Interrupt Vectors
    5. 7.5 FRAM and the FRAM Controller
      1. 7.5.1 Flash and FRAM Overview Comparison
      2. 7.5.2 Cache Architecture
  9. 8 Peripheral Considerations
    1. 8.1  Watchdog Timer
    2. 8.2  Ports
      1. 8.2.1 Digital Input/Output
      2. 8.2.2 Capacitive Touch I/O
    3. 8.3  Analog-to-Digital Converters
      1. 8.3.1 ADC10 to ADC
    4. 8.4  Communication Modules
      1. 8.4.1 USI to eUSCI
      2. 8.4.2 USCI to eUSCI
    5. 8.5  Timer and IR Modulation Logic
    6. 8.6  Backup Memory
    7. 8.7  Hardware Multiplier (MPY32)
    8. 8.8  RTC Counter
    9. 8.9  Interrupt Compare Controller (ICC)
    10. 8.10 LCD
    11. 8.11 Smart Analog Combo (SAC)
    12. 8.12 Comparator
  10. 9 ROM Libraries
  11. 10Conclusion
  12. 11References
  13. 12Revision History

8.4.2 USCI to eUSCI

The architecture and the internal state machine of the eUSCI in the FR4xx family are very similar to the USCI module in the F2xx family. However, there are many new features added in the eUSCI as well as changes made to the existing features. While most of the code is still compatible, TI recommends reviewing the register names. Table 8-2 shows most of the significant differences between the families. For more detailed information, see Migrating from the USCI module to the eUSCI module [8].

Table 8-2 Comparison of USCI and eUSCI Modules
Parameter or FeatureUSCI (F2xx)eUSCI (FR4xx)
UART
Enhanced baud rate generationNoYes
TXEPT interrupt (similar to USART)NoYes
Start edge interruptNoYes
Selectable glitch filterNoYes
Interrupt vector generatorNoYes
SPI
Enhanced baud rate generationNoYes
Maximum baud rate4 to 6 MHz5 MHz(1)
Interrupt vector generatorNoYes
I2C
Preload of transmit bufferNoYes
Clock low timeoutNoYes
Byte counterNoYes
Multiple slave addressingNoYes
Address bit maskNoYes
Hardware clear of interrupt flagsYesNo
Interrupt vector generatorNoYes
(1) Calculated based on SPI timing with another MSP430FR4133 device in slave mode. For the formula to calculate the maximum baud rate, see the device-specific data sheet.

The eUSCI_A module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. The eUSCI_B module provides support for SPI (3 or 4 pin) and I2C.

Another significant difference for the eUSCI module in most FR4xx devices (except for the MSP430FR231x, MSP430FR211x, MSP430FR231x, MSP430FR235x, MSP430FR215x, MSP430FR267x, and MSP430FR247x) is that there is no ACLK available for the clock source. If the eUSCI clock source does not support ACLK, the eUSCI cannot work in LPM3 mode. See the clock distribution table in the device-specific data sheet for details. A workaround to allow UART or I2C to work in LPM3 mode is to route the ACLK output to the UCA0CLK or UCB0CLK pin externally. This workaround costs two GPIO pins, and it is available only with package that include an output for the ACLK signal. In MSP430FR231x devices, clock distribution is changed so that ACLK is available for the eUSCI module.

The FR4xx devices have eUSCI_A and eUSCI_B modules. See the device-specific data sheet for the number of instances of each module. Table 8-3 summarizes the pin configurations for the communication interfaces.

In MSP430FR231x devices, a pin remapping function is available for eUSCI_B0. The USCIBRMP bit in SYSCFG2 register controls eUSCI_B0 pins remapping from P1.0–P1.3 to P2.2–P2.5. Only one port can be selected and valid at one time.

In MSP430FR211x devices, the pin remapping functions are available for eUSCI_A and Timer_B. The USCIARMP bit in the SYSCFG3 register controls eUSCI_A pin remapping from P1.4–P1.7 to P1.0–P1.3. The TBRMP bit in the SYSCFG3 register controls Timer_B output pin remapping from P1.6–P1.7 to P2.0–P2.1. Only one port can be selected and valid at one time.

Table 8-3 FR4xx eUSCI Pin Configurations
eUSCI_A0Pin of FR413x or FR203xPin of FR2433, FR263x, or FR253xPin of FR231xPin of FR21xx or FR2000Pin of FR235x or FR215xPin of FR267x or FR247xUARTSPI
P1.0P1.4P1.7P1.7, P1.3P1.7P1.4(1),
P5.
2(2)		TXDSIMO
P1.1P1.5P1.6P1.6, P1.2P1.6P1.5(1),
P5.1(2)		RXDSOMI
P1.2P1.6P1.5P1.5, P1.1P1.5P1.6(1),
P5.0(2)		–SCLK
P1.3P1.7P1.4P1.4, P1.0P1.4P1.7(1),
P4.7(2)		–STE
eUSCI_A1Pin of FR413x or FR203xPin of FR2433, FR263x, or FR253xPin of FR231xPin of FR21xx or FR2000Pin of FR235x or FR215xPin of FR267x or FR247xUARTSPI
Not availableP2.6Not availableNot availableP4.3P2.6TXDSIMO
P2.5P4.2P2.5RXDSOMI
P2.4P4.1P2.4–SCLK
P3.1P4.0P3.1–STE
eUSCI_B0Pin of FR413x or FR203xPin of FR2433, FR263x, or FR253xPin of FR231xPin of FR21xx or FR2000Pin of FR235x or FR215xPin of FR267x or FR247xI2CSPI
P5.0P1.0P1.0, P2.2Not availableP1.0P1.0(1),
P5.6(2)		–STE
P5.1P1.1P1.1, P2.3P1.1P1.1(1),
P5.5(2)		–SCLK
P5.2P1.2P1.2, P2.4P1.2P1.2(1),
P4.6(2)		SDASIMO
P5.3P1.3P1.3, P2.5P1.3P1.3(1),
P4.5(2)		SCLSOMI
eUSCI_B1Pin of FR413x or FR203xPin of FR2433, FR263x, or FR253xPin of FR231xPin of FR21xx or FR2000Pin of FR235x or FR215xPin of FR267x or FR247xI2CSPI
Not availableNot availableNot availableNot availableP4.4P2.7(1),
P5.4(2)		–STE
P4.5P3.5(1),
P5.3(2)		–SCLK
P4.6P3.2(1),
P4.4(2)		SDASIMO
P4.7P3.6(1),
P4.3(2)		SCLSOMI
(1) This is the mappable default function that is controlled by the USCIBRMP or USCIARMP bit of the SYSCFG2 or SYCFG3 register. Only one selected port is valid at any time.
(2) This is the mappable function that is controlled by the USCIBRMP or USCIARMP bit of the SYSCFG2 or SYCFG3 register. Only one selected port is valid at any time.