SLAAEF9A November   2023  – May 2025 MSPM0C1104 , MSPM0G3507 , MSPM0H3216 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1306 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of Renesas RL78 MCUs to MSPM0 MCUs
  5. 2Ecosystem And Migration
    1. 2.1 Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 The IDE Supported By MSPM0
      3. 2.1.3 SysConfig
      4. 2.1.4 Debug Tools
      5. 2.1.5 LaunchPad™
    2. 2.2 Migration Process
      1. 2.2.1 Step 1: Choose The Right MSPM0 MCU
      2. 2.2.2 Step 2. Set Up IDE And Quick Introduction of CCS
        1. 2.2.2.1 Set Up IDE
        2. 2.2.2.2 Quick Introduction of CCS
      3. 2.2.3 Step 3: Set Up MSPM0 SDK And Quick Introduction of MSPM0 SDK
        1. 2.2.3.1 Set Up MSPM0 SDK
        2. 2.2.3.2 Quick Introduction of SDK
      4. 2.2.4 Step 4: Software Evaluation
      5. 2.2.5 Step 5. PCB Board Design
      6. 2.2.6 Step 6. Mass Production
    3. 2.3 Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Flash Memory Regions
        2. 3.2.2.2 NONMAIN Memory of MSPM0
        3. 3.2.2.3 Flash Memory Registers of RL78
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power-up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
      1. 3.4.1 Oscillators
        1. 3.4.1.1 MSPM0 Oscillators
      2. 3.4.2 Clock Signal Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Modes
      3. 3.5.3 Entering Lower-Power Modes
      4. 3.5.4 Low-Power Mode Code Examples
    6. 3.6 Interrupts and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
        1. 3.6.1.1 Interrupt Management of RL78
        2. 3.6.1.2 Interrupt Management of MSPM0
      2. 3.6.2 Event Handler of MSPM0
      3. 3.6.3 Event Link Controller (ELC) of RL78
      4. 3.6.4 Event Management Comparison
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Debug Comparison
      2. 3.7.2 Programming Mode Comparison
        1. 3.7.2.1 Bootstrap Loader (BSL) Programming of MSPM0
        2. 3.7.2.2 Serial Programming (Using External Device) of RL78
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 Inter-Integrated Circuit (I2C)
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6Summary
  10. 7References
  11. 8Revision History

5.3 Digital-to-Analog Converter (DAC)

The RL78 and MSPM0 family of parts both offer 12-bit, 8-bit DAC peripherals to perform digital to analog conversion for various applications. In RL78 documentation, 12-bit DAC is referred to as the 12-bit D/A converter and 8-bit DAC is referred to as the DAC, D/A Converter. The 12-bit D/A converter is only available on the RL78 I1E and L1A families of devices. In MSPM0, the 12-bit DAC peripheral is referred to as the DAC12. This differentiates the DAC12 from the 8-bits DACs that are available for use with each comparator peripheral included in a given MSPM0 device. Those additional 8-bit DACs are covered in the comparator section of this document. This DAC12 peripheral is only available on the MSPM0G family of devices.

The features of the 12-bit DAC peripherals for the RL78 and MSPM0G are summarized in Table 5-4.

MSPM0L and C DAC is intergrated in the COMP. MSPM0H series and MSPM0C1103, MSPM0C1104 do not have COMP, thus there is no DAC supported.

Table 5-4 DAC Feature Set Comparison
Feature RL78 MSPM0G MSPM0L/C
Resolution 12 bits 12 bits (11 ENOB) 8 bit
Output rate 33 kSPS 1 MSPS 1 MSPS
Output channels 2 (1) 1 (2) 1
Data formats 12-bit right aligned, 12-bit left aligned 8-bit right aligned, 12-bit right aligned, two's complement or straight binary 8-bit right aligned
DMA integration Yes (DTC) Yes Yes
Output routing External Pins External Pins Internal peripheral connections: OPA IN+, COMP IN+
Internal peripheral connections: OPA IN+, COMP IN+, ADC0
Internal reference voltage Yes, 1.48V Yes, 2.5V or 1.4V Yes, 2.5V or 1.4V
External reference voltage Yes Yes No
FIFO No Yes No
Output buffer No Yes No
Configurable output offset No Yes No
Self-calibration mode No Yes No
Trigger sources Event link Internal dedicated sample time generator, DMA interrupts/events, FIFO threshold interrupts/events, two hardware triggers (available from event fabric) Event
(1) Available only on L1A device with 12 bits resolution.
(2) Dual DAC channels are planned for future MSPM0G devices.

DAC12 Code Examples: information about DAC12 code examples can be found in the MSPM0 SDK examples guide.