SLAAEF9A November   2023  – May 2025 MSPM0C1104 , MSPM0G3507 , MSPM0H3216 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1306 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of Renesas RL78 MCUs to MSPM0 MCUs
  5. 2Ecosystem And Migration
    1. 2.1 Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 The IDE Supported By MSPM0
      3. 2.1.3 SysConfig
      4. 2.1.4 Debug Tools
      5. 2.1.5 LaunchPad™
    2. 2.2 Migration Process
      1. 2.2.1 Step 1: Choose The Right MSPM0 MCU
      2. 2.2.2 Step 2. Set Up IDE And Quick Introduction of CCS
        1. 2.2.2.1 Set Up IDE
        2. 2.2.2.2 Quick Introduction of CCS
      3. 2.2.3 Step 3: Set Up MSPM0 SDK And Quick Introduction of MSPM0 SDK
        1. 2.2.3.1 Set Up MSPM0 SDK
        2. 2.2.3.2 Quick Introduction of SDK
      4. 2.2.4 Step 4: Software Evaluation
      5. 2.2.5 Step 5. PCB Board Design
      6. 2.2.6 Step 6. Mass Production
    3. 2.3 Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Flash Memory Regions
        2. 3.2.2.2 NONMAIN Memory of MSPM0
        3. 3.2.2.3 Flash Memory Registers of RL78
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power-up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
      1. 3.4.1 Oscillators
        1. 3.4.1.1 MSPM0 Oscillators
      2. 3.4.2 Clock Signal Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Modes
      3. 3.5.3 Entering Lower-Power Modes
      4. 3.5.4 Low-Power Mode Code Examples
    6. 3.6 Interrupts and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
        1. 3.6.1.1 Interrupt Management of RL78
        2. 3.6.1.2 Interrupt Management of MSPM0
      2. 3.6.2 Event Handler of MSPM0
      3. 3.6.3 Event Link Controller (ELC) of RL78
      4. 3.6.4 Event Management Comparison
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Debug Comparison
      2. 3.7.2 Programming Mode Comparison
        1. 3.7.2.1 Bootstrap Loader (BSL) Programming of MSPM0
        2. 3.7.2.2 Serial Programming (Using External Device) of RL78
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 Inter-Integrated Circuit (I2C)
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6Summary
  10. 7References
  11. 8Revision History

3.6.1 Interrupts and Exceptions

The MSPM0 and RL78 both register and map interrupt and exception vectors depending on the available peripherals of the device. A summary and comparison of the interrupt vectors for each family of devices is included in Table 3-11. A lower value of priority for an interrupt or exception is given higher precedence over interrupts with a higher priority value. When the processor is currently handling an interrupt, the processor can only be preempted by an interrupt with high programmable priority.

Table 3-11 Interrupts Comparison
Features RL78 MSPM0x
Interrupt Types Maskable: determined by devices and divided into internal interrupt and external interrupt. Peripheral interrupts: NVIC of MSPM0G supports up to 32 peripheral interrupt vectors NVIC of MSPM0L supports up to 19 peripheral interrupt vectorsNVIC of MSPM0C supports up to 23 peripheral interrupt vectorsMSPM0H supports up to 22 peripheral interrupt vectors(1).
Reset: determined by devices Reset, NMI, Hard Fault, SVCall, PendSV, SysTick
Priority Level The default priority level: determined by devices (2) The default priority level: NVIC Number (3)
The maskable interrupts have 4 programmable priority levels: 0, 1, 2, 3 System exceptions (Reset, NMI, Hard Fault) have fixed priority levels of -3, -2, and -1
The peripheral interrupts have 4 programmable priority levels: 0, 64, 128, 192
Priority Set PR0xy and PR1xy registers: used to set the maskable interrupt priority level IPRx registers in the NVIC: used to set the peripheral interrupt priority level
Interrupt mask MKxy registers: used to enable/disable the corresponding maskable interrupt IMASK register in the peripheral side: used to configure which interrupt conditions propagate into an event (4)
ISER and ICER register in the NVIC: used to enable or disable the peripheral interrupts
(1) In addition to the NVIC, interrupt grouping modules (INT_GROUP0 and INT_GROUP1) can be present on a MSPM0 device to enable interfacing of more than 32 peripheral interrupts to the NVIC.
(2) The default priority indicates the relative interrupt priority if multiple maskable interrupts have the same programmable priority.
(3) The NVIC number indicates the relative interrupt priority if multiple NVIC interrupts have the same programmable priority.
(4) The event handler and related management registers of MSPM0 are shown in Section 3.6.2.