SLAAEF9A November   2023  – May 2025 MSPM0C1104 , MSPM0G3507 , MSPM0H3216 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1306 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of Renesas RL78 MCUs to MSPM0 MCUs
  5. 2Ecosystem And Migration
    1. 2.1 Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 The IDE Supported By MSPM0
      3. 2.1.3 SysConfig
      4. 2.1.4 Debug Tools
      5. 2.1.5 LaunchPad™
    2. 2.2 Migration Process
      1. 2.2.1 Step 1: Choose The Right MSPM0 MCU
      2. 2.2.2 Step 2. Set Up IDE And Quick Introduction of CCS
        1. 2.2.2.1 Set Up IDE
        2. 2.2.2.2 Quick Introduction of CCS
      3. 2.2.3 Step 3: Set Up MSPM0 SDK And Quick Introduction of MSPM0 SDK
        1. 2.2.3.1 Set Up MSPM0 SDK
        2. 2.2.3.2 Quick Introduction of SDK
      4. 2.2.4 Step 4: Software Evaluation
      5. 2.2.5 Step 5. PCB Board Design
      6. 2.2.6 Step 6. Mass Production
    3. 2.3 Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Flash Memory Regions
        2. 3.2.2.2 NONMAIN Memory of MSPM0
        3. 3.2.2.3 Flash Memory Registers of RL78
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power-up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
      1. 3.4.1 Oscillators
        1. 3.4.1.1 MSPM0 Oscillators
      2. 3.4.2 Clock Signal Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Modes
      3. 3.5.3 Entering Lower-Power Modes
      4. 3.5.4 Low-Power Mode Code Examples
    6. 3.6 Interrupts and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
        1. 3.6.1.1 Interrupt Management of RL78
        2. 3.6.1.2 Interrupt Management of MSPM0
      2. 3.6.2 Event Handler of MSPM0
      3. 3.6.3 Event Link Controller (ELC) of RL78
      4. 3.6.4 Event Management Comparison
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Debug Comparison
      2. 3.7.2 Programming Mode Comparison
        1. 3.7.2.1 Bootstrap Loader (BSL) Programming of MSPM0
        2. 3.7.2.2 Serial Programming (Using External Device) of RL78
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 Inter-Integrated Circuit (I2C)
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6Summary
  10. 7References
  11. 8Revision History

3.5.1 Operating Modes Comparison

Table 3-10 gives a brief comparison between RL78 and MSPM0 devices.

Table 3-10 Operating Modes Comparison Between RL78 and MSPM0 Devices
RL78 MSPM0
Operation Mode Description Operation Mode Description
MAIN RUN CPU operates on main system clock(1) CPU, clock, and peripherals work RUN 0 MCLK and CPUCLK run from a fast clock source (SYSOSC, HFCLK, or SYSPLL)
CPU operates on subsystem clock CPU, clock, and peripherals work 1 MCLK and CPUCLK run from LFCLK (at 32kHz).
2
HALT CPU operates on main system clock(1) CPU operation stops. Operation of main system clock continues. Status of subsystem clock is retained. Most peripheral functions can operate. SLEEP 0 CPU operation stops. SYSOSC remains enable and other high-speed oscillators are optional. Low-speed oscillators remains enable. MCLK run from a fast clock source.
N/A N/A 1 CPU operation stops. SYSOSC remains enable and other high-speed oscillators are disable. Low-speed oscillators remains enable. MCLK run from LFCLK.
CPU operates on subsystem clock CPU operation stops. Operation of main system clock stops. Operation of subsystem clock continues. Most peripheral functions can operate. 2 CPU operation stops. High-speed oscillators are disable. Low-speed oscillators remains enable. MCLK run from LFCLK.
SNOOZE(2) (3) CPU operation stops. fHOCO/ fIH operation starts, fX,fEX and fPLL operation stop. The status of subsystem clock while used in the STOP mode continues. Peripheral functions such as ADC, UART or CSI can operate without operating the CPU. STOP 0 CPU operation stops. Status of SYSOSC is retained. Other high-speed oscillators are disable. Low-speed oscillators remains enable. ULPCLK is limited to 4MHz. PD0 is enabled and PD1 is disabled. Analog peripherals such as ADC can operate.
1 Same as STOP0, with the SYSOSC and ULPCLK gear shifted to 4MHz
N/A 2 CPU operation stops. High-speed oscillators are disable. ULPCLK runs at 32kHz. PD0 is enabled and PD1 is disabled. The use of ADC is not supported.
N/A N/A STANDBY 0 CPU operation stops. High-speed oscillators are disable. All PD0 peripherals receive the ULPCLK and LFCLK. ADC is not supported.
1 Similar to STANDBY0, with only TIMG0/1 receiving ULPCLK or LFCLK.
STOP(3) CPU operation stops. Operation of main system clock stops. The status of subsystem clock before STOP mode was set is retained. The whole system stops. SHUTDOWN No clocks are available and device is shut down.
(1) CPU can operate on fIH/fHOCO, fX, fEX or fPLL.
(2) The SNOOZE mode can only be specified when the high-speed on-chip oscillator is selected for the CPU or peripheral hardware clock (fCLK).
(3) The SNOOZE mode can only be specified for CSI, UART and the A/D converter, and so forth. In the case of CSI or UART data reception, an A/D conversion request by the timer trigger signal, and so forth, MCU is gear shifted from the STOP mode to the SNOOZE mode. Then, the CSI or UART data is received without operating the CPU, A/D conversion is performed, and so forth.