SLAU948B October 2024 – March 2025 MSPM0G3507
Table 5-4 shows the register to control Algorithm debug functions.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | CLEAR_FAULT | W | 0b | Bit to clear set controller and Gate Driver Faults.
Bit is automatically reset. 1h = Clear Fault Command. |
| 30-0 | Reserved | R | 0000000000b | Reserved |