SLLSFW3A April   2025  – June 2025 SN55LVTA4-SEP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Unused Enable Pins
      2. 7.3.2 Driver Disabled Output
      3. 7.3.3 Driver Equivalent Schematics
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Detailed Design Procedure
          1. 8.1.1.1.1 Interconnecting Media
        2. 8.1.1.2 Design Requirements
        3. 8.1.1.3 Application Curve
      2. 8.1.2 Cold Sparing
      3. 8.1.3 Power Supply Recommendations
        1. 8.1.3.1 Supply Bypass Capacitance
      4. 8.1.4 Layout
        1. 8.1.4.1 Layout Guidelines
          1. 8.1.4.1.1 Microstrip vs. Stripline Topologies
          2. 8.1.4.1.2 Dielectric Type and Board Construction
          3. 8.1.4.1.3 Recommended Stack Layout
          4. 8.1.4.1.4 Separation Between Traces
          5. 8.1.4.1.5 Crosstalk and Ground Bounce Minimization
        2. 8.1.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Related Documentation
  11. 10Receiving Notification of Documentation Updates
  12. 11Support Resources
  13. 12Trademarks
  14. 13Electrostatic Discharge Caution
  15. 14Glossary
  16. 15Revision History
  17. 16Mechanical, Packaging, and Orderable Information

Supply Bypass Capacitance

Bypass capacitors play a key role in power distribution circuitry. Specifically, bypass capacitors create low-impedance paths between power and ground at particular frequency depending on the value. At low frequencies, a voltage regulator offers low-impedance paths between the terminal and ground. However, as higher frequency currents propagate through power traces, the source is quite often incapable of maintaining a low-impedance path to ground. Bypass capacitors are used to address this shortcoming. Usually, large bypass capacitors (10µF to 1000μF) at the board-level do a good job up into the kHz range. Due to the size and length of the leads, large capacitors tend to have large inductance values at the switching frequencies of modern digital circuitry. To solve this problem, one can resort to the use of smaller capacitors (nF to μF range) installed locally next to the integrated circuit.

Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass capacitors in high-speed environments, because the lead inductance is about 1nH. For comparison purposes, a typical capacitor with leads has a lead inductance around 5nH.

The value of the bypass capacitors used locally with LVDS chips can be determined by the following formula, equations Equation 1 to Equation 2. A conservative rise time of 200ps and a worst-case change in supply current of 1A covers the whole range of LVDS devices offered by Texas Instruments. In this example, the maximum power supply noise tolerated is 200mV; however, this figure varies depending on the noise budget available in your design.

Equation 1. C c h i p   =   I M a x i m u m   S t e p   C h a n g e   S u p p l y   C u r r e n t V M a x i m u m   P o w e r   S u p p l y   N o i s e   ×   T R i s e   T i m e
Equation 2. C L V D S   =   1 A 0.2 V   ×   200   p s   =   0.001   μ F

The following example lowers lead inductance and covers intermediate frequencies between the board-level capacitor (>10µF) and the value of capacitance found above (0.001µF). The smallest value of capacitance shall be as close as possible to the chip.

SN55LVTA4-SEP Recommended LVDS Bypass Capacitor Layout Figure 8-4 Recommended LVDS Bypass Capacitor Layout