SLLSFW3A April   2025  – June 2025 SN55LVTA4-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Unused Enable Pins
      2. 7.3.2 Driver Disabled Output
      3. 7.3.3 Driver Equivalent Schematics
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Detailed Design Procedure
          1. 8.1.1.1.1 Interconnecting Media
        2. 8.1.1.2 Design Requirements
        3. 8.1.1.3 Application Curve
      2. 8.1.2 Cold Sparing
      3. 8.1.3 Power Supply Recommendations
        1. 8.1.3.1 Supply Bypass Capacitance
      4. 8.1.4 Layout
        1. 8.1.4.1 Layout Guidelines
          1. 8.1.4.1.1 Microstrip vs. Stripline Topologies
          2. 8.1.4.1.2 Dielectric Type and Board Construction
          3. 8.1.4.1.3 Recommended Stack Layout
          4. 8.1.4.1.4 Separation Between Traces
          5. 8.1.4.1.5 Crosstalk and Ground Bounce Minimization
        2. 8.1.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
  11. 10Receiving Notification of Documentation Updates
  12. 11Support Resources
  13. 12Trademarks
  14. 13Electrostatic Discharge Caution
  15. 14Glossary
  16. 15Revision History
  17. 16Mechanical, Packaging, and Orderable Information

5.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
tr Differential output rise time (20% to 80%) RL = 100Ω, CL= 10pF input tr,tf= 1ns, 200MHz clock pattern, input VIL=0.8V VIH=V VCC = 3V to 3.6V 0.4 0.5 1 ns
tf Differential output fall time (80% to 20%) VCC = 3V to 3.6V 0.4 0.5 1 ns
tPHL Propagation delay time, high-to-low-level output RL = 100Ω, CL= 10pF input tr,tf= 1ns, 200MHz clock pattern, input VIL=0.8V VIH=2V VCC = 3V to 3.6V 0.5 1.7 4.5 ns
tPLH Propagation delay time, low-to-high-level output RL = 100Ω, CL= 10pF input tr,tf= 1ns, 200MHz clock pattern, input VIL=0.8V VIH=2V VCC = 3V to 3.6V 1 1.4 4 ns
tSK(P) Pulse skew, |tPHL – tPLH| RL = 100Ω, CL= 10pF input tr,tf= 1ns, 200MHz clock pattern, input VIL=0.8V VIH=2V VCC = 3V to 3.6V 0.3 0.6 ns
tSK(O) Chanel to channel output skew, |tPHL to tPHL| or |tPLH to tPLH| RL = 100Ω, CL= 10pF input tr,tf= 1ns, 200MHz clock pattern, input VIL=0.8V VIH=2V VCC = 3V to 3.6V 0.3 0.6 ns
F(max) Maximum operating frequency RL = 100Ω, CL= 10pF input tr,tf= 1ns, 200MHz clock pattern, input VIL=0.8V VIH=2V VCC = 3V to 3.6V 200 MHz
tPHZ Disable time, 1.4V input to 50% output RL = 100Ω, CL= 10pF input tr,tf= 1ns, 1MHz clock pattern on enable, input VIL=0.8V VIH=2V VCC = 3V to 3.6V 8.1 17 ns
tPLZ Disable time, 1.4V input to 50% output RL = 100Ω, CL= 10pF input tr,tf= 1ns, 1MHz clock pattern on enable, input VIL=0.8V VIH=2V 7.3 15 ns
tPZH Enable time, 1.4V input to 50% output RL = 100Ω, CL= 10pF input tr,tf= 1ns, 1MHz clock pattern on enable, input VIL=0.8V VIH=2V 5.4 15 ns
tPZL Enable time, 1.4V input to 50% output RL = 100Ω, CL= 10pF input tr,tf= 1ns, 1MHz clock pattern on enable, input VIL=0.8V VIH=2V 2.5 15 ns