SLLSFW3A April   2025  – June 2025 SN55LVTA4-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Unused Enable Pins
      2. 7.3.2 Driver Disabled Output
      3. 7.3.3 Driver Equivalent Schematics
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Detailed Design Procedure
          1. 8.1.1.1.1 Interconnecting Media
        2. 8.1.1.2 Design Requirements
        3. 8.1.1.3 Application Curve
      2. 8.1.2 Cold Sparing
      3. 8.1.3 Power Supply Recommendations
        1. 8.1.3.1 Supply Bypass Capacitance
      4. 8.1.4 Layout
        1. 8.1.4.1 Layout Guidelines
          1. 8.1.4.1.1 Microstrip vs. Stripline Topologies
          2. 8.1.4.1.2 Dielectric Type and Board Construction
          3. 8.1.4.1.3 Recommended Stack Layout
          4. 8.1.4.1.4 Separation Between Traces
          5. 8.1.4.1.5 Crosstalk and Ground Bounce Minimization
        2. 8.1.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
  11. 10Receiving Notification of Documentation Updates
  12. 11Support Resources
  13. 12Trademarks
  14. 13Electrostatic Discharge Caution
  15. 14Glossary
  16. 15Revision History
  17. 16Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 D Package, 16-Pin SOIC (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
1A 1 I LVTTL input signal, 300kΩ internal pull down
1Y 2 O Differential (LVDS) non-inverting output
1Z 3 O Differential (LVDS) inverting output
G 4 I Enable (HI = ENABLE) (must not be left floating)
2Z 5 O Differential (LVDS) inverting output
2Y 6 O Differential (LVDS) non-inverting output
2A 7 I LVTTL input signal, 300kΩ internal pull down
GND 8 G Ground
3A 9 I LVTTL input signal, 300kΩ internal pull down
3Y 10 O Differential (LVDS) non-inverting output
3Z 11 O Differential (LVDS) inverting output
G 12 I Enable (LO = ENABLE) (must not be left floating)
4Z 13 O Differential (LVDS) inverting output
4Y 14 O Differential (LVDS) non-inverting output
4A 15 I LVTTL input signal, 300kΩ internal pull down
VCC 16 P Supply voltage
(1) Signal Types: I = Input, O = Output, I/O = Input or Output, P= Power, G=Ground