SLLSFW3A April   2025  – June 2025 SN55LVTA4-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Unused Enable Pins
      2. 7.3.2 Driver Disabled Output
      3. 7.3.3 Driver Equivalent Schematics
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Detailed Design Procedure
          1. 8.1.1.1.1 Interconnecting Media
        2. 8.1.1.2 Design Requirements
        3. 8.1.1.3 Application Curve
      2. 8.1.2 Cold Sparing
      3. 8.1.3 Power Supply Recommendations
        1. 8.1.3.1 Supply Bypass Capacitance
      4. 8.1.4 Layout
        1. 8.1.4.1 Layout Guidelines
          1. 8.1.4.1.1 Microstrip vs. Stripline Topologies
          2. 8.1.4.1.2 Dielectric Type and Board Construction
          3. 8.1.4.1.3 Recommended Stack Layout
          4. 8.1.4.1.4 Separation Between Traces
          5. 8.1.4.1.5 Crosstalk and Ground Bounce Minimization
        2. 8.1.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
  11. 10Receiving Notification of Documentation Updates
  12. 11Support Resources
  13. 12Trademarks
  14. 13Electrostatic Discharge Caution
  15. 14Glossary
  16. 15Revision History
  17. 16Mechanical, Packaging, and Orderable Information
8.1.4.1.3 Recommended Stack Layout

Following the choice of dielectrics and design specifications, the user should decide how many levels to use in the stack. To reduce the TTL/CMOS to LVDS crosstalk, a good practice is to have at least two separate signal planes as shown in Figure 8-7.

SN55LVTA4-SEP Four-Layer PCB BoardFigure 8-7 Four-Layer PCB Board
Note:

The separation between layers 2 and 3 should be 127μm (0.005in). By keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients.

One of the most common stack configurations is the six-layer board, as shown in Figure 8-8.

SN55LVTA4-SEP Six-Layer PCB BoardFigure 8-8 Six-Layer PCB Board

In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer board is preferable, because it offers the layout designer more flexibility in varying the distance between signal layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.