SLLSFW3A April   2025  – June 2025 SN55LVTA4-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Unused Enable Pins
      2. 7.3.2 Driver Disabled Output
      3. 7.3.3 Driver Equivalent Schematics
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Detailed Design Procedure
          1. 8.1.1.1.1 Interconnecting Media
        2. 8.1.1.2 Design Requirements
        3. 8.1.1.3 Application Curve
      2. 8.1.2 Cold Sparing
      3. 8.1.3 Power Supply Recommendations
        1. 8.1.3.1 Supply Bypass Capacitance
      4. 8.1.4 Layout
        1. 8.1.4.1 Layout Guidelines
          1. 8.1.4.1.1 Microstrip vs. Stripline Topologies
          2. 8.1.4.1.2 Dielectric Type and Board Construction
          3. 8.1.4.1.3 Recommended Stack Layout
          4. 8.1.4.1.4 Separation Between Traces
          5. 8.1.4.1.5 Crosstalk and Ground Bounce Minimization
        2. 8.1.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
  11. 10Receiving Notification of Documentation Updates
  12. 11Support Resources
  13. 12Trademarks
  14. 13Electrostatic Discharge Caution
  15. 14Glossary
  16. 15Revision History
  17. 16Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
VOD Driver differential output voltage RL = 100 Ω 247 340 454 mV
Δ|VOD| Change in differential output voltage between logic states RL = 100Ω –50 50 mV
VOC(SS) Steady statte common-mode output voltage RL = 100Ω 1.125 1.2 1.375 V
ΔVOC(SS) Change in steady-state common-mode output voltage RL = 100Ω –50 50 mV
VOC(PP) Peak-to-peak common-mode output voltage RL = 100Ω 50 mV
IO(OFF) Output current with power off VCC = 0 , VO = 2.4V –4 4 µA
IOZ High impedance state output current VO = 0 or 2.4V, G = 0.8V and G = 2V –1 1 µA
IOS Short-circuit output current, Y or Z VO = 0V -4 -24 mA
IOS Short-circuit output current, Y & Z VOD = 0V -12 12 mA
Input
VIH High level input voltage ( G, G, A) VCC = 3V to 3.6V 2 V
VIL Low level input voltage (G, G, A) VCC = 3V to 3.6V 0.8 V
IIH High level input current ( G) VIH = 3.6V, VCC = 0V or 3.6V 4 20 µA
IIL Low level input current ( G) VIL = 0V, VCC = 0V or 3.6V 0.1 10 µA
IIH High level input current (G) VIH = 3.6V, VCC = 0V or 3.6V 4 20 µA
IIL Low level input current (G) VIL = 0V, VCC = 0V or 3.6V 0.1 10 µA
IIH High level input current (A) VIH = 3.6V, VCC = 0V or 3.6V 4 20 µA
IIL Low level input current (A) VIL = 0V, VCC = 0V or 3.6V 0.1 10 µA
CI Input Capacitance (G, G, A) to ground VCC = 0V to 3.6V 5 pF
Supply
ICC Supply current  VI = VCC or GND, No load, enabled -55°C < TA < 125°C 9 20 mA
VI = VCC or GND, RL = 100Ω, enabled -55°C < TA < 125°C 25 35 mA
ICC Supply current (quiescent) VI = VCC or GND, No load, disabled -55°C < TA < 125°C 0.25 1 mA