SLUSFQ8B December   2024  – June 2025 BQ2969T

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Details
        1. 7.3.1.1 Input Sense Voltage, Vx
        2. 7.3.1.2 Output Drive, OUT
        3. 7.3.1.3 Supply Input, VDD
        4. 7.3.1.4 Control / PTC Input Pin, CTL
        5. 7.3.1.5 Regulated Supply Output, REG
      2. 7.3.2 Overvoltage Sensing for OUT
      3. 7.3.3 Regulator Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 NORMAL Mode
      2. 7.4.2 OVERVOLTAGE Mode
      3. 7.4.3 UNDERVOLTAGE Mode
      4. 7.4.4 CTL / OVERTEMPERATURE Mode
      5. 7.4.5 CUSTOMER TEST MODE
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 CTL for PTC Thermistor Protection
      5. 8.2.5 CTL for External OUT Overdrive
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.4.4 CTL / OVERTEMPERATURE Mode

The CTL / OVERTEMPERATURE mode is entered if the voltage on the CTL pin falls below the VDD–VCTL threshold for the tUVDELAY. The OUT pin is asserted after the tUVDELAY, which is pre-programmed by TI. The OUT pin is typically used to then enable an external FET and blow a fuse to disable the pack.

The CTL pin can be used as a control input from external circuitry to cause the OUT pin to be asserted. The pin can also be used to implement cell overtemperature protection by connecting a PTC thermistor between the VDD and CTL pins of the device. The device includes an internal pulldown resistance from the CTL pin to VSS, with a resistance configured by TI. The pulldown resistance is enabled periodically when the CTL pin level is evaluated by the device. As the PTC resistance increases, this resistive divider with the internal pulldown resistance causes the CTL pin voltage to fall below the VDD–VCTL threshold, resulting in the CTL / OVERTEMPERATURE mode being triggered and the OUT pin being asserted.

When the CTL / OVERTEMPERATURE mode is triggered, the OUT pin remains asserted until the CTL pin voltage rises above the VDD–VCTL threshold. While in CTL / OVERTEMPERATURE mode, the internal pulldown resistance is reduced to half the normal value. When a PTC is used for cell overtemperature protection, this causes a temperature hysteresis, so the CTL / OVERTEMPERATURE mode only exits when the PTC thermistor reduces to a lower resistance.

If the latch option is configured in the device, then the OUT pin latches asserted when the CTL / OVERTEMPERATURE mode is triggered. The Undervoltage Detection Delay used to trigger the CTL / OVERTEMPERATURE mode is reduced to tDELAY_CTM while the device is in Customer Test Mode.

When the CTL pin voltage rises above the VDD–VCTL threshold, the device returns to NORMAL mode if the output is not configured to latch when asserted. The regulated output remains enabled in this mode if all cell voltages are above VUVREG.