SLUSFQ8B December   2024  – June 2025 BQ2969T

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Details
        1. 7.3.1.1 Input Sense Voltage, Vx
        2. 7.3.1.2 Output Drive, OUT
        3. 7.3.1.3 Supply Input, VDD
        4. 7.3.1.4 Control / PTC Input Pin, CTL
        5. 7.3.1.5 Regulated Supply Output, REG
      2. 7.3.2 Overvoltage Sensing for OUT
      3. 7.3.3 Regulator Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 NORMAL Mode
      2. 7.4.2 OVERVOLTAGE Mode
      3. 7.4.3 UNDERVOLTAGE Mode
      4. 7.4.4 CTL / OVERTEMPERATURE Mode
      5. 7.4.5 CUSTOMER TEST MODE
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 CTL for PTC Thermistor Protection
      5. 8.2.5 CTL for External OUT Overdrive
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

Typical values stated where TA = 25°C and VDD = 15.2V, MIN/MAX values stated where TA = –40°C to 110°C, and VDD = 3V to 22V (unless otherwise noted).
PARAMETER PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Voltage Protection
Thresholds
VOV V(PROTECT) Overvoltage Detection RIN = 1kΩ Applicable Voltage: 3.6V to 5.2V V
VOVHYST OV Detection Hysteresis Nominal setting of 150mV 100 150 200 mV
Nominal setting of 300mV 250 300 350 mV
VOA OV Detection Accuracy TA = 25°C –12 12 mV
VOADRIFT OV Detection Accuracy Across Temperature(1) TA = –40°C –40 40 mV
TA = -10°C –22 22 mV
TA = 55°C –24 24 mV
TA = 85°C –37 37 mV
TA = 110°C –50 50 mV
Supply and
Leakage Current
IDD Supply Current in NORMAL mode (Vn – Vn-1) = (V1 – VSS) = 3.8V, n = 2, 3, 4, VDD = 15.2V, IREG = 0mA, TA = –10°C to 60°C 1.23 2 µA
(Vn – Vn-1) = (V1 – VSS) = 3.8V, n = 2, 3, 4, VDD = 15.2V, IREG = 0mA, TA = –40°C to 110°C 2.5 µA
Supply Current in UV (Vn - Vn-1) = 3.8V, n = 2, 3, 4, and VUVQUAL < (V1 - VSS) < VUVREG, VDD = 11.4V, TA = –10°C to 60°C 0.25 0.5 µA
(Vn - Vn-1) = 3.8V, n = 2, 3, 4, and VUVQUAL < (V1 - VSS) < VUVREG, VDD = 11.4V, TA = -40°C to 110°C 0.7 µA
Supply Current in OV (Vn - Vn-1) = 3.8V, n = 2, 3, 4, and VOV < (V1 - VSS), VDD = 15.2V, TA = -40°C to 110°C 15 33 µA
IIN Input Current at Vn Pins (Vn – Vn-1) = (V1 – VSS) = 3.8V, n = 2, 3, 4, VDD = 15.2V, TA = 25°C –0.1 0.1 µA
Input Voltage
VCTL CTL Input Voltage Threshold VDD – CTL, VDD ≥ 5V, TA = –40°C to 85°C 2.55 2.8 2.95 V
VDD – CTL, VDD ≥ 5V, TA = –40°C to 110°C 2.55 2.8 3.37 V
tCTLDELAY CTL Delay(3) VDD ≥ 5V 5.2 6.5 7.8 s
RPD CTL internal pulldown resistance CTL = VDD; 500kΩ, 1MΩ, 2MΩ, 10MΩ options -30 30 %
RPDH CTL hysteresis internal pulldown resistance VDD – CTL > VCTL; RPDH ≈ RPD / 2, VDD ≥ 5V ±30 %
OUT Pin Driver
VOUT Output Drive Voltage OUT pin configured in active high mode, (Vn – Vn-1) or (V1 – VSS) > VOV, n = 2, 3, 4, IOH = 100µA, VDD ≥ 7.5V  5.5 8 V
OUT pin configured in active high mode, (Vn – Vn-1) or (V1 – VSS) > VOV, n = 2, 3, 4, IOH = 100µA, 3V < VDD < 7.5V  VDD – 1.5 VDD – 1.1 VDD V
OUT pin configured in active high mode, (Vn – Vn-1) and (V1 – VSS) < VOV, n = 2, 3, 4, IOL = 100µA flowing into OUT pin. 190 400 mV
IOUTH OUT Source Current (during OV) OUT pin configured in active high mode, (Vn – Vn-1) or (V1 – VSS) > VOV, n = 2, 3, 4, OUT = 0V, current measured sourced from OUT pin. 0.6 5.2 mA
IOUTL OUT Sink Current OUT pin configured in active high, open-drain active pulldown, or open-drain inactive pulldown.  Device output in pulldown state, OUT driven to 0.5V, current measured into OUT pin.   0.2 4 mA
OV Delay Timer
tDELAY OV Delay Time(2) Internal fixed delay, 0.25 second delay option(3) 0.14 0.25 0.38 s
Internal fixed delay, 0.5 second delay option(3) 0.34 0.5 0.68 s
Internal fixed delay, 1 second delay option(3) 0.74 1 1.28 s
Internal fixed delay, 2 second delay option(3) 1.54 2 2.48 s
Internal fixed delay, 3 second delay option(3) 2.4 3 3.6 s
Internal fixed delay, 4 second delay option(3) 3.2 4 4.8 s
Internal fixed delay, 5.5 second delay option(3) 4.4 5.5 6.6 s
Internal fixed delay, 6.5 second delay option(3) 5.2 6.5 7.8 s
tDELAY_CTM OV Delay Time in Test Mode Internal fixed delay 15 ms
tDELAY_RESET OV Delay Reset Time With one cell voltage above VOV, others cells below VOV, minimum time the high cell voltage must fall below VOV to reset OV Delay Timer(3) 0.1 ms
Regulated
Supply Output, REG
VREG REG Supply VDD ≥ 7.5V, IREG = 10µA, CREG = 0.47µF, VREG = 3.8V, TA = 25°C 3.724 3.8 3.876 V
VDD ≥ 4V, IREG = 10µA, CREG = 0.47µF, VREG = 3.3V, TA = 25°C 3.234 3.3 3.366 V
VDD ≥ 4V, IREG = 10µA, CREG = 0.47µF, VREG = 3.15V, TA = 25°C 3.087 3.15 3.213 V
VDD ≥ 4V, IREG = 10µA, CREG = 0.47µF, VREG = 3.0V, TA = 25°C 2.94 3.0 3.06 V
VDD ≥ 3V, IREG = 10µA, CREG = 0.47µF, VREG = 2.5V, TA = 25°C 2.45 2.5 2.55 V
VDD ≥ 3V, IREG = 10µA, CREG = 0.47µF, VREG = 1.8V, TA = 25°C 1.764 1.8 1.836 V
VDD ≥ 3V, IREG = 10µA, CREG = 0.47µF, VREG = 1.5V, TA = 25°C 1.470 1.5 1.530 V
VREG REG Supply VDD ≥ 7.5V, IREG = 3mA, CREG = 0.47µF, VREG = 3.8V 3.58 3.8 3.88 V
VDD ≥ 4V, IREG = 3mA, CREG = 0.47µF, VREG = 3.3V 3.12 3.3 3.39 V
VDD ≥ 4V, IREG = 3mA, CREG = 0.47µF, VREG = 3.15V 2.98 3.15 3.23 V
VDD ≥ 4V, IREG = 3mA, CREG = 0.47µF, VREG = 3.0V 2.84 3.0 3.08 V
VDD ≥ 3V, IREG = 3mA, CREG = 0.47µF, VREG = 2.5V 2.35 2.5 2.57 V
VDD ≥ 3V, IREG = 3mA, CREG = 0.47µF, VREG = 1.8V 1.70 1.8 1.85 V
VDD ≥ 3V, IREG = 3mA, CREG = 0.47µF, VREG = 1.5V 1.42 1.5 1.56 V
IREG_ SC_Limit REG Output Short Circuit Current Limit REG = VSS, CREG = 0.47µF 3.2 25 mA
RREG_ PD REG pull-down resistor Activated when REG is disabled 20 30 40 kΩ
Regulated Supply Undervoltage Self-disable
VUVREG Undervoltage detection accuracy Factory Configuration: 1.0V to 4.15V in 50mV steps, TA = 25 °C –50 50 mV
VUVHYS Undervoltage detection hysteresis 250 300 350 mV
tUVDELAY Undervoltage detection delay(3) 5.2 6.5 7.8 s
VUVQUAL Cell voltage to qualify for UV detection 0.45 0.5 0.55 V
(1) Specified by a combination of characterization and production test
(2) Delay values specified when transitioning from NORMAL mode to OVERVOLTAGE mode.  While device is in UNDERVOLTAGE mode, the delay can increase by a value between 0 and 1.2 seconds.
(3) Specified by a combination of design and production test