SLVSGZ9A February   2025  – May 2025 TPS4141-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions TPS4141-Q1
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Ratings
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Uni-directional Voltage Sensing
      2. 6.3.2 Bi-directional Voltage Sensing
      3. 6.3.3 Bi-directional and Uni-directional Voltage Sensing
      4. 6.3.4 High Voltage Input Range
      5. 6.3.5 Calculating the Output Voltage (VAOUT)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Divider Ratio Selection
        2. 7.2.2.2 Error Estimation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

7.2.2.2 Error Estimation

The following error sources are used to estimate the total measurement error:

  • TPS4141-Q1 HV input offset error, VOFFSET_HV, ±240mV.
  • TPS4141-Q1 HV gain error, GAINERROR, ±0.25%.
  • ADC absolute accuracy, ADCACC. For BQ79731-Q1, ±1.5mV.

For uni-directional operation, Equation 3 is used to estimate the maximum and minimum AOUT voltage for a full scale range of VHV = 1000V, DIVNOM = 320V/V, and VREF = 0V:

Equation 7. V A O U T = 1 ± 0.0025 × 1000 V ± 0.24 V 320
Equation 8. V A O U T _ M A X = 3.13356 V         V A O U T _ M I N = 3.11644 V

The AOUT voltage with no error source contribution (VAOUT_IDEAL) can be found using Equation 1 with VREF = 0V:

Equation 9. V A O U T _ I D E A L = 1000 V 320 = 3.125 V

Using VAOUT_MAX, VAOUT_MIN, and VAOUT_IDEAL, the total full scale range percentage error is ±0.274%. This may also be found by directly using Equation 6:

Equation 10. % E R R O R R E L = ± 100 % × 1 + 0.25 100 × 1 + 0.24 1000 - 1 = ± 0.274 %

The ADC measurement error at full scale range is:

Equation 11. % E R R O R A D C = ± 100 % × 1.5 m V 3.125 V = ± 0.048 %

Adding these error contributions leads to a total estimated error of ±0.322%.