SLVSGZ9A February   2025  – May 2025 TPS4141-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions TPS4141-Q1
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Ratings
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Uni-directional Voltage Sensing
      2. 6.3.2 Bi-directional Voltage Sensing
      3. 6.3.3 Bi-directional and Uni-directional Voltage Sensing
      4. 6.3.4 High Voltage Input Range
      5. 6.3.5 Calculating the Output Voltage (VAOUT)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Divider Ratio Selection
        2. 7.2.2.2 Error Estimation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

5.6 Electrical Characteristics

Unless otherwise noted, all minimum/maximum specifications are over recommended operating conditions. All typical values are measured at TJ = 25℃, VVDD = 5V, VCE = 5V, CAOUT = 47nF, RAOUT = 200Ω.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PRECISION RESISTOR DIVIDER AND AMPLIFIER
RTOTAL Resistance from HV to HVGND or HV to REF. 25 30 37 MΩ
DIVNOM Nominal divide ratio DIV1 = L, DIV0 = L
 160 V/V
DIV1 = L, DIV0 = H
 320 V/V
DIV1 = H, DIV0 = L
 640 V/V
DIV1 = H, DIV0 = H
 1000 V/V
GAINERROR(1)(2) DIV = 160V/V setting.
Nominal gain = 1/DIV.		 TJ = 25°C
 –0.15 0.15 %
 
–40°C ≤ TJ ≤ 150°C
 –0.25 0.25 %
 
DIV = 320V/V setting.
Nominal gain = 1/DIV.		 TJ = 25°C
 –0.15 0.15 %
 
–40°C ≤ TJ ≤ 150°C
 –0.25 0.25 %
DIV = 640V/V setting.
Nominal gain = 1/DIV.		 TJ = 25°C
 –0.15 0.15 %
 
–40°C ≤ TJ ≤ 150°C
 –0.25 0.25 %
DIV = 1000V/V setting.
Nominal gain = 1/DIV.		 TJ = 25°C
 –0.15 0.15 %
 
–40°C ≤ TJ ≤ 150°C
 –0.25 0.25 %
VOFFSET_HV Measurement offset voltage referred to HV input.
 –40°C ≤ TJ ≤ 150°C –240 240 mV
CMRAIN Amplifier common mode input range 0 3.0 V
CMRAOUT Amplifier common mode output range 0 4.1 V
BWHV_REF Measurement bandwidth - HV to AOUT, REF to AOUT DIV = 160 7 kHz
DIV = 320 14 kHz
DIV = 640 30 kHz
DIV =1000 53 kHz
SUPPLY (VDD)
VUVLO_R VDD undervoltage threshold rising VDD rising 4 4.2 4.4 V
VUVLO_F VDD undervoltage threshold falling VDD falling 3.9 4.1 4.3 V
VUVLO_HYS VDD undervoltage threshold hysteresis 160 mV
IVDD_ON VDD current, device powered on TJ = 25°C 4 mA
–40°C ≤ TJ ≤ 150°C 4 7.5 mA
IVDD_OFF VDD current, device powered off VVDD = 5V, VCE = 0V, TJ = 25°C
 4 7 µA
VVDD = 5V, VCE = 0V, –40°C ≤ TJ ≤ 150°C
 48 µA
VVDD = 20V, VCE = 0V, TJ = 25°C 8 15 µA
VVDD = 20V, VCE = 0V, –40°C ≤ TJ ≤ 150°C
 60
SWITCH CHARACTERISTICS
IOFF Off leakage CE = L,
VHV = 1200V, TJ = 25°C		 0.02 0.15 µA
CE = L,
VHV = 1200V, TJ = 85°C		 0.5
CE = L,
VHV = 1200V, TJ = 105°C		 1
CE = L,
VHV = 1200V, TJ = 125°C		 5
CE = L,
VHV = 1200V, –40°C ≤ TJ ≤ 150°C		 30
BVVDSS Switch breakdown voltage. IHV = 8µA, TJ = 25°C
CE = L		 1270 1550 V
IHV = 30µA, –40°C ≤ TJ ≤ 150°C
CE = L		 1270 1550 V
COSS HV capacitance VHV = 0V, f = 1MHz 2 pF
LOGIC-LEVEL INPUT (CE, DIV0, DIV1)
VIL, CE Chip enable input logic low voltage 0.0 0.8 V
VIH, CE Chip enable input logic high voltage 2.4 20.0 V
VHYS, CE Chip enable input logic hysteresis 225 mV
VIL, DIVx DIV0/DIV1 input logic for low state 0.8 V
VIM, DIVx DIV0/DIV1 input logic for mid state 1.3 1.8 V
VIH, DIVx DIV0/DIV1 input logic for high state 2.4 V
VHYS, DIVx DIV0/DIV1 input logic hysteresis. 180 mV
IIL_CE Input logic low current VCE = 0V –0.1 0.1 µA
VCE = 0.8V 1.3 2.3 4 µA
IIH_CE Input logic high current VCE = 5V 6.5 11 20 µA
VCE = 20V 6.6 12 22 µA
IIL_DIVx Input logic low current VDIVx = 0V –23 –14 –8 µA
VDIVx = 0.8V –11 –7 –4 µA
IIM_DIVx Input logic mid current VDIVx = 1.3V –4 –2 –1 µA
VDIVx = 1.8V 1.3 2.4 5 µA
IIH_DIVx Input logic high current VDIVx = 2.4V 4 8 23 µA
VDIVx = 5V 9 17 32 µA
VDIVx = 20V 9 17 32 µA
RPD_CE Pull down resistance on CE 200 360 580 kΩ
RPU_DIVx Pull up resistance on DIV0, DIV1 200 360 580 kΩ
RPD_DIVx Pull down resistance on DIV0, DIV1 80 165 375 kΩ
(1) Computed gain error (%) = 100 × [DIVnom (VAOUT,HV_max – VAOUT,HV_min) / (VHV_max – VHV_min) – 1]
(2) Refer to High Voltage Input Range for VHV input ranges supported for uni-directional and bi-directional operation.