SLVSIO8 September 2026 TPS638221
PRODMIX
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| SUPPLY | ||||||||
| VIN | Input voltage range | 1.8 | 5.5 | V | ||||
| VIT+ | Positive-going UVLO threshold voltage | 1.8 | 1.9 | 2.0 | V | |||
| VIT- | Negative-going UVLO threshold | 1.6 | 1.7 | 1.8 | V | |||
| VHYS | Hysteresis voltage | 200 | mV | |||||
| IQ | Quiescent current into VIN | VIN = 3.6V, VEN = 3.6V, VOUT = 3.3V, non-switching, TJ = –40°C to 85°C |
2.3 | 4 | µA | |||
| IQ | Quiescent current into VOUT | VIN = 3.6V, VEN = 3.6V, VOUT = 3.3V, non-switching, TJ = –40°C to 85°C |
0.3 | 1 | µA | |||
| ISD | Shutdown current into VIN | VIN = 3.6V, VOUT = 0V, VEN = 0V TJ = –40°C to 85°C |
0.3 | 2.5 | µA | |||
| I/O SIGNALS | ||||||||
| VIT+ | Positive-going input threshold voltage | MODE, EN | 0.82 | V | ||||
| VIT– | Negative-going input threshold voltage | MODE, EN | 0.33 | V | ||||
| VIM | Mid-level input voltage | MODE | 0.6 | V | ||||
| IIH | High-level input current | MODE | VMODE = 1.2V | 0.01 | 0.1 | µA | ||
| IIL | Low-level input current | MODE | VMODE = 0V | 0.01 | 0.1 | µA | ||
| IIB | Input bias current | EN | VEN = 0V to 5.5V | 2.5 | 30 | nA | ||
| REN | EN pin pulldown resistor | EN = low | 800 | kΩ | ||||
| POWER STAGE | ||||||||
| VO | Output voltage range | 1.2 | 5.5 | V | ||||
| VREF | Feedback Regulation Voltage | 0.792 | 0.800 | 0.808 | V | |||
| PFM valley - DC offset | PFM operation | 0.7 | 1.5 | 2.5 | % | |||
| DC offset | Ultra-sonic operation, VOUT ≥ 2.5V | 0.7 | 1.25 | 2.5 | % | |||
| IFB_lkg | Leakage current at FB pin | 50 | nA | |||||
| Valley switching current limit | 5.7 | 6.5 | 7 | A | ||||
| Reverse valley switching current limit | -4.0 | -3.3 | -2 | A | ||||
| Hysteresis current | 800 | mA | ||||||
| Buck side RDS(on) | High-side MOSFET on resistance on buck side | 11.6 | mΩ | |||||
| Low-side MOSFET on resistance on buck side | 15.5 | |||||||
| Boost side RDS(on) | High-side MOSFET on resistance on boost side | 11.6 | ||||||
| Low-side MOSFET on resistance on boost side | 15.3 | |||||||
| Ilkg | Leakage current into VIN to LX1 | EN = GND, VIN=5.5V, VLX1=0V, TJ = –40°C to 85°C | 0.03 | 4 | µA | |||
| Ilkg | Leakage current into VOUT to LX2 | EN = GND, VOUT=5.5V, VLX2=0V, TJ = –40°C to 85°C | 0.03 | 4 | µA | |||
| Ilkg | Leakage current into LX1 to GND | EN = GND, VLX1=5.5V, TJ = –40°C to 85°C | 0.02 | 4 | µA | |||
| Ilkg | Leakage current into LX2 to GND | EN = GND, VLX2=5.5V, TJ = –40°C to 85°C | 0.02 | 4 | µA | |||
| IDISCHG | Output discharge current | VIN = 3.0V | 160 | mA | ||||
| TIMING PARAMETER | ||||||||
| tSS | Soft-start time | 0.2 | 0.3 | 0.4 | mS | |||
| td(EN) | Delay between a rising edge on the EN pin and the start of output voltage ramp | 200 | 240 | µS | ||||
| Switching frequency at ultra-sonic mode | 24 | kHz | ||||||
| PROTECTION | ||||||||
| VT+(IVP) | Input OVP threshold voltage | 5.65 | 5.75 | 5.95 | V | |||
| Input OVP hysteresis | 100 | mV | ||||||
| VT+(OVP) | Output OVP threshold voltage | 5.65 | 5.75 | 5.95 | V | |||
| Output OVP hysteresis | 100 | mV | ||||||
| VPG_TH_rising | Power good threshold for rising | 95 | % | |||||
| VPG_TH_falling | Power good threshold for falling | 90 | % | |||||
| VPG_low | Power good low level output voltage | 0.36 | V | |||||
| Ilkg | PG pin leakage current | 0.03 | µA | |||||
| hiccup on time | 2 | mS | ||||||
| hiccup off time | 74 | mS | ||||||
| Thermal shutdown threshold temperature | TJ rising | 165 | °C | |||||
| Thermal shutdown hysteresis | 20 | °C | ||||||