SLVSIR8 June   2026 TPS61383-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VCC Power Supply and UVLO Logic
        1. 6.3.1.1 Internal VCC
      2. 6.3.2 Enable or Shutdown
      3. 6.3.3 Spread Spectrum
      4. 6.3.4 STATUS Pin
        1. 6.3.4.1 Status Indicatior IO (STATUS Pin)
        2. 6.3.4.2 Configured as External PMOS Driver
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Charger Feature Description
        1. 6.4.1.1 Charger Enable
        2. 6.4.1.2 LDO Charger and Buck Charger Description
          1. 6.4.1.2.1 Buck Charger
          2. 6.4.1.2.2 LDO Charger
        3. 6.4.1.3 NiMH Battery Charging Profile
          1. 6.4.1.3.1 Manual Charge Mode
        4. 6.4.1.4 Lithium Battery Charging Profile
        5. 6.4.1.5 Super Capacitor Charging Profile
        6. 6.4.1.6 Battery Cold, Hot Temperature (TS Pin)
        7. 6.4.1.7 Charger Protection and Fault Condition Indication
      2. 6.4.2 Boost Feature Description
        1. 6.4.2.1 Enable and Start-Up
          1. 6.4.2.1.1 Automatic Transition into Boost Mode
          2. 6.4.2.1.2 Manual Transition into Boost Mode
        2. 6.4.2.2 Down Mode
        3. 6.4.2.3 Output Short-to-Ground Protection
        4. 6.4.2.4 Boost Control Loop
        5. 6.4.2.5 Current Limit Operation
        6. 6.4.2.6 Functional Modes at Light Load
          1. 6.4.2.6.1 Auto PFM Mode
          2. 6.4.2.6.2 Forced PWM Mode
        7. 6.4.2.7 Duty Cycle Limitation
        8. 6.4.2.8 BUB Voltage Loop
      3. 6.4.3 Battery State-of-Health (SOH) Detection Mode Description
        1. 6.4.3.1 SOH Mode Operation
        2. 6.4.3.2 Multi-Signal Output in AVI Pin
        3. 6.4.3.3 Calculate Resistance of Super Capacitor
        4. 6.4.3.4 Calculate Capacitance of Super Capacitor
    5. 6.5 Programming I2C Serial Interface
      1. 6.5.1 Data Validity
      2. 6.5.2 START and STOP Conditions
      3. 6.5.3 Byte Format
      4. 6.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 6.5.5 Target Address and Data Direction Bit
      6. 6.5.6 Single Read and Write
      7. 6.5.7 Multi-Read and Multi-Write
  8. 7 Register Maps
    1. 7.1  Register 00H: CHIP_ID
    2. 7.2  Register 01H: BOOST_SET1
    3. 7.3  Register 02H: BOOST_SET2
    4. 7.4  Register 03H: BOOST_SET3
    5. 7.5  Register 04H: CHGR_SET1
    6. 7.6  Register 05H: CHGR_SET2
    7. 7.7  Register 06H: CHGR_SET3
    8. 7.8  Register 07H: CHGR_SET4
    9. 7.9  Register 08H: CHGR_STATUS
    10. 7.10 Register 09H: SOH_SET1
    11. 7.11 Register 0AH: SOH_SET2
    12. 7.12 Register 0BH: CONTROL_STATUS
    13. 7.13 Register 0CH: FAULT_CONDITION
    14. 7.14 Register 0DH: STATUS_PIN_SET
    15. 7.15 Register 0EH: SW_RST
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the External MOSFET
        2. 8.2.2.2 Selecting the External Schottky
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Capacitor in Super Capacitor Side
        5. 8.2.2.5 Selecting the Output Capacitor
        6. 8.2.2.6 Loop Stability and Compensation Design
          1. 8.2.2.6.1 Small Signal Analysis
          2. 8.2.2.6.2 Loop Compensation Design
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.14 Register 0DH: STATUS_PIN_SET

Figure 7-24 STATUS_PIN_SET
76543210
INC_BSTINC_ABSTINC_ADNINC_TSDINC_TSFAULT

STATUS_OR_DRV

DRV_CONTROLDRV_OUT
R-1bR-0bR-0bR-0bR-0bR/W-0bR/W-0bR/W-0b
Figure 7-25 STATUS_PIN_SET Register Field Descriptions
BitFieldTypeResetDescription

[7]

INC_BST

R/W

1

0= BST_ACTIVE status is not included in the STATUS pin output

1= BST_ACTIVE status is included in the STATUS pin output, STATUS pin pulls low when entering boost mode

Check Section 7.12 for descriptions of BST_ACTIVE signal

[6]

INC_ABST

R/W

0

0= ALRT_BST_ACTIVE status is not included in the STATUS pin output, STATUS pin pulls low when boost mode is entered since last read

1= ALRT_BST_ACTIVE status is included in the STATUS pin output

Check Section 7.12 for descriptions of ALRT_BST_ACTIVE signal

[5]

INC_ADN

R/W

0

0= ALRT_CHGR_MODE_DONE status is not included in the STATUS pin output, STATUS pin pulls low when charger operation is done since last read

1= ALRT_CHGR_MODE_DONE status is included in the STATUS pin output

Check Section 7.9 for descriptions of ALRT_CHGR_MODE_DONE signal

[4]

INC_TSD

R/W

0

0= THRM_SD status is not included in the STATUS pin output, STATUS pin pulls low when thermal shutdown is triggered

1= THRM_SD status is included in the STATUS pin output

Check Section 7.13 for descriptions of THRM_SD signal

[3]

INC_TSFAULT

R/W

0

0= TS_FAULT status is not included in the STATUS pin output, STATUS pin pulls low when TS_FAULT is triggered

1= TS_FAULT status is included in the STATUS pin output

Check Section 7.13 for descriptions of TS_FAULT signal

[2]

STATUS_OR_DRV

R/W

0

0= Pin 8 operates as an open-drain digital output to indicate the IC status

1= Pin 8 operates as an external PMOS driver

[1]

DRV_CONTROLR/W0This bit configures external PMOS driver logic. Only availible when STATUS_OR_DRV is 1

0= Automatic control on external PMOS driver. Turn on PMOS when boost mode is not active. Shut off PMOS when entering boost mode.

1= Automatic control on external PMOS driver. Turn on PMOS when DRV_OUT bit is 1. Shut off PMOS when DRV_OUT bit is 0.

[0]

DRV_OUTR/W0This bit configures external PMOS driver output manually. Only availible when STATUS_OR_DRV is 1 and DRV_CONTROL bit is 1.

0= Turn off external PMOS

1= Turn on external PMOS