SNAS512K September   2011  – October 2025 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VCC and VCCO Power Supplies
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock Inputs
      2. 8.4.2 Clock Outputs
        1. 8.4.2.1 Reference Output
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Driving the Clock Inputs
        2. 9.2.1.2 Crystal Interface
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Termination and Use of Clock Drivers
          1. 9.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 9.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 9.2.2.1.3 Termination for Single-Ended Operation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Sequencing
      2. 9.3.2 Current Consumption and Power Dissipation Calculations
        1. 9.3.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
        2. 9.3.2.2 Power Dissipation Example #2: Worst-Case Dissipation
      3. 9.3.3 Power Supply Bypassing
        1. 9.3.3.1 Power Supply Ripple Rejection
      4. 9.3.4 Thermal Management
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.3.2 Current Consumption and Power Dissipation Calculations

The current consumption values specified in Electrical Characteristics can be used to calculate the total power dissipation and IC power dissipation for any device configuration. Use Equation 6 to calculate the total VCC core supply current (ICC_TOTAL):

Equation 6. ICC_TOTAL = ICC_CORE + ICC_BANK_A + ICC_BANK_B + ICC_CMOS

where

  • ICC_CORE is the current for core logic and input blocks and depends on selected input (CLKinX or OSCin).
  • ICC_BANK_A is the current for Bank A and depends on output type (ICC_PECL, ICC_LVDS, ICC_HCSL, or 0mA if disabled).
  • ICC_BANK_B is the current for Bank B and depends on output type (ICC_PECL, ICC_LVDS, ICC_HCSL, or 0mA if disabled).
  • ICC_CMOS is the current for the LVCMOS output (or 0mA if REFout is disabled).

Since the output supplies (VCCOA, VCCOB, VCCOC) can be powered from 3 independent voltages, the respective output supply currents (ICCO_BANK_A, ICCO_BANK_B, ICCO_CMOS) must be calculated separately.

ICCO_BANK for either Bank A or B can be directly taken from the corresponding output supply current specification (ICCO_PECL, ICCO_LVDS, or ICCO_HCSL) provided the output loading matches the specified conditions. Otherwise, ICCO_BANK must be calculated as follows:

Equation 7. ICCO_BANK = IBANK_BIAS + (N × IOUT_LOAD)

where

  • IBANK_BIAS is the output bank bias current (fixed value).
  • IOUT_LOAD is the DC load current per loaded output pair.
  • N is the number of loaded output pairs in the bank (N = 0 to 5).

Table 9-1 shows the typical IBANK_BIAS values and IOUT_LOAD expressions for the three differential output types.

For LVPECL, using a larger termination resistor (RT) to ground instead of terminating with 50Ω to VTT = VCCO – 2V is possible; this technique is commonly used to eliminate the extra termination voltage supply (VTT) and potentially reduce device power dissipation at the expense of lower output swing. For example, when VCCO is 3.3V, a RT value of 160Ω to ground eliminates the 1.3V termination supply without sacrificing much output swing. In this case, the typical IOUT_LOAD is 25mA, so ICCO_PECL for a fully-loaded bank reduces to 158mA (versus 165mA with 50Ω resistors to VCCO – 2V).

Table 9-1 Typical Output Bank Bias and Load Currents
CURRENT PARAMETERLVPECLLVDSHCSL
IBANK_BIAS33mA34mA6mA
IOUT_LOAD(VOH - VTT)/RT + (VOL - VTT)/RT0mA (No DC load current)VOH/RT

When the current consumption is calculated or known for each supply, the total power dissipation (PTOTAL) can be calculated as:

Equation 8. PTOTAL = (VCC × ICC_TOTAL) + (VCCOA × ICCO_BANK_A) + (VCCOB × ICCO_BANK_B) + (VCCOC × ICCO_CMOS)

If the device configuration has LVPECL or HCSL outputs, then calculating the power dissipated in any termination resistors (PRT_ PECL and PRT_HCSL) and in any termination voltages (PVTT) is also necessary. The external power dissipation values can be calculated as follows:

Equation 9. PRT_PECL (per LVPECL pair) = (VOH - VTT)2/RT + (VOL - VTT)2/RT
Equation 10. PVTT_PECL (per LVPECL pair) = VTT * [(VOH - VTT)/RT + (VOL - VTT)/RT]
Equation 11. PRT_HCSL (per HCSL pair) = VOH2 / RT

Finally, the IC power dissipation (PDEVICE) can be computed by subtracting the external power dissipation values from PTOTAL as follows:

Equation 12. PDEVICE = PTOTAL – N1 × (PRT_PECL + PVTT_PECL) – N2 × PRT_HCSL

where

  • N1 is the number of LVPECL output pairs with termination resistors to VTT (typically Vcco - 2V or GND).
  • N2 is the number of HCSL output pairs with termination resistors to GND.