Power dissipation in the LMK00301 device can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature must be limited to a maximum of 125°C. That is, as an estimate, T_A (ambient temperature) plus device power dissipation times R _θJA must not exceed 125°C.

The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to provide adequate heat conduction out of the package.

A recommended land and via pattern is shown in Figure 9-18. More information on soldering WQFN packages can be obtained at: http://www.ti.com/packaging.

Figure 9-18 Recommended Land and Via Pattern

To minimize junction temperature, use a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area can be plated or solder coated to prevent corrosion but must not have conformal coating (if possible), which can provide thermal insulation. The vias shown in Figure 9-18 must connect these top and bottom copper layers and to the ground layer. These vias act as “heat pipes” to carry the thermal energy away from the device side of the board to where heat can be more effectively dissipated.