SNAS512K September   2011  – October 2025 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VCC and VCCO Power Supplies
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock Inputs
      2. 8.4.2 Clock Outputs
        1. 8.4.2.1 Reference Output
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Driving the Clock Inputs
        2. 9.2.1.2 Crystal Interface
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Termination and Use of Clock Drivers
          1. 9.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 9.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 9.2.2.1.3 Termination for Single-Ended Operation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Sequencing
      2. 9.3.2 Current Consumption and Power Dissipation Calculations
        1. 9.3.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
        2. 9.3.2.2 Power Dissipation Example #2: Worst-Case Dissipation
      3. 9.3.3 Power Supply Bypassing
        1. 9.3.3.1 Power Supply Ripple Rejection
      4. 9.3.4 Thermal Management
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6 Typical Characteristics

Unless otherwise specified: VCC = 3.3V, VCCO = 3.3V, TA = 25°C, CLKin driven differentially, input slew rate ≥ 3V/ns. Consult Table 6-1 at the end of Typical Characteristics for graph notes.

LMK00301 LVPECL Output Swing (VOD) vs Frequency
Figure 6-1 LVPECL Output Swing (VOD) vs Frequency
LMK00301 HCSL Output Swing (VOD) vs Frequency
Figure 6-3 HCSL Output Swing (VOD) vs Frequency
LMK00301 LVDS Output Swing at 156.25MHz
Figure 6-5 LVDS Output Swing at 156.25MHz
LMK00301 LVDS Output Swing at 1.5GHz
Figure 6-7 LVDS Output Swing at 1.5GHz
LMK00301 LVCMOS Output Swing at 250MHz
Figure 6-9 LVCMOS Output Swing at 250MHz
LMK00301 Noise Floor vs CLKin Slew Rate at 156.25MHz
Figure 6-11 Noise Floor vs CLKin Slew Rate at 156.25MHz
LMK00301 RMS Jitter vs CLKin Slew Rate at 100MHz
See Note 1 in Graph Notes table
Figure 6-13 RMS Jitter vs CLKin Slew Rate at 100MHz
LMK00301 RMS Jitter vs CLKin Slew Rate at 625MHz
Figure 6-15 RMS Jitter vs CLKin Slew Rate at 625MHz
LMK00301 PSRR vs Ripple Frequency at 312.5MHz
Figure 6-17 PSRR vs Ripple Frequency at 312.5MHz
LMK00301 Crystal Power Dissipation vs RLIM
See Notes 2 and 3 in Graph Notes table
Figure 6-19 Crystal Power Dissipation vs RLIM
LMK00301 LVDS Output Swing (VOD) vs Frequency
Figure 6-2 LVDS Output Swing (VOD) vs Frequency
LMK00301 LVPECL Output Swing at 156.25MHz
Figure 6-4 LVPECL Output Swing at 156.25MHz
LMK00301 LVPECL Output Swing at 1.5GHz
Figure 6-6 LVPECL Output Swing at 1.5GHz
LMK00301 HCSL Output Swing at 250MHz
Figure 6-8 HCSL Output Swing at 250MHz
LMK00301 Noise Floor vs CLKin Slew Rate at 100MHz
Figure 6-10 Noise Floor vs CLKin Slew Rate at 100MHz
LMK00301 Noise Floor vs CLKin Slew Rate at 625MHz
Figure 6-12 Noise Floor vs CLKin Slew Rate at 625MHz
LMK00301 RMS Jitter vs CLKin Slew Rate at 156.25MHz
See Note 1 in Graph Notes table
Figure 6-14 RMS Jitter vs CLKin Slew Rate at 156.25MHz
LMK00301 PSRR vs Ripple Frequency at 156.25MHz
Figure 6-16 PSRR vs Ripple Frequency at 156.25MHz
LMK00301 Propagation Delay vs Temperature
Figure 6-18 Propagation Delay vs Temperature
LMK00301 LVDS Phase Noise in Crystal Mode
See Notes 2 and 3 in Graph Notes table
Figure 6-20 LVDS Phase Noise in Crystal Mode
LMK00301 HCSL Phase Noise at 100MHz
See Note 1 in Graph Notes table
Figure 6-21 HCSL Phase Noise at 100MHz
LMK00301 LVDS Phase Noise at 100MHz
See Note 1 in Graph Notes table
Figure 6-22 LVDS Phase Noise at 100MHz
LMK00301 LVPECL Phase Noise at 100MHz
See Note 1 in Graph Notes table
Figure 6-23 LVPECL Phase Noise at 100MHz
Table 6-1 Graph Notes
NOTE
(1) The typical RMS jitter values in the plots show the total output RMS jitter (JOUT) for each output buffer type and the source clock RMS jitter (JSOURCE). From these values, the Additive RMS Jitter can be calculated as: JADD = SQRT(JOUT2 – JSOURCE2).
(2) 20MHz crystal characteristics: Abracon ABL series, AT cut, CL = 18pF , C0 = 4.4pF measured (7pF maximum), ESR = 8.5Ω measured (40Ω maximum), and Drive Level = 1mW maximum (100µW typical).
(3) 40MHz crystal characteristics: Abracon ABLS2 series, AT cut, CL = 18pF , C0 = 5pF measured (7pF maximum), ESR = 5Ω measured (40Ω maximum), and Drive Level = 1mW maximum (100µW typical).