SNAS512K September   2011  – October 2025 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VCC and VCCO Power Supplies
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock Inputs
      2. 8.4.2 Clock Outputs
        1. 8.4.2.1 Reference Output
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Driving the Clock Inputs
        2. 9.2.1.2 Crystal Interface
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Termination and Use of Clock Drivers
          1. 9.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 9.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 9.2.2.1.3 Termination for Single-Ended Operation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Sequencing
      2. 9.3.2 Current Consumption and Power Dissipation Calculations
        1. 9.3.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
        2. 9.3.2.2 Power Dissipation Example #2: Worst-Case Dissipation
      3. 9.3.3 Power Supply Bypassing
        1. 9.3.3.1 Power Supply Ripple Rejection
      4. 9.3.4 Thermal Management
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.3.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs

This example shows how to calculate IC power dissipation for a configuration with separate VCC and VCCO supplies and unused outputs. Because some outputs are not used, the ICCO_PECL value specified in Electrical Characteristics cannot be used directly, and output bank current (ICCO_BANK) must be calculated to accurately estimate the IC power dissipation.

  • VCC = 3.3V, VCCOA = 3.3V, VCCOB = 2.5V. Typical ICC and ICCO values.
  • CLKin0/CLKin0* input is selected.
  • Bank A is configured for LVPECL: 4 pairs used with RT = 50Ω to VT = VCCO – 2V (1 pair unused).
  • Bank B is configured for LVDS: 3 pairs used with RL = 100Ω differential (2 pairs unused).
  • REFout is disabled.
  • TA = 85°C

Using the current and power calculations from the previous section, we can compute PTOTAL and PDEVICE.

  • From Equation 6: ICC_TOTAL = 8.5mA + 20mA + 26mA + 0mA = 54.5mA
  • From Table 9-1: IOUT_LOAD (LVPECL) = (1.6V – 0.5V) 50Ω + (0.75V – 0.5V)/50Ω = 27mA
  • From Equation 7: ICCO_BANK_A = 33mA + (4 × 27mA) = 141mA
  • From Equation 8: PTOTAL = (3.3V × 54.5mA) + (3.3V × 141mA) + (2.5V × 34mA)] = 730mW
  • From Equation 9: PRT_PECL = ((2.4V – 1.3V)2/50 Ω) + ((1.55V – 1.3V)2/50 Ω) = 25.5mW (per output pair)
  • From Equation 10: PVTT_PECL = 0.5V × [ ((2.4V – 1.3V) / 50Ω) + ((1.55V – 1.3V) / 50Ω) ] = 13.5mW (per output pair)
  • From Equation 11: PRT_HCSL = 0mW (no HCSL outputs)
  • From Equation 12: PDEVICE = 730mW – (4 × (25.5mW + 13.5mW)) – 0mW = 574mW

In this example, the IC device dissipates about 574mW or 79% of the total power (730mW), while the remaining 21% is dissipated in the emitter resistors (102mW for 4 pairs) and termination voltage (54mW into VCCO – 2V).

Based on the thermal resistance junction-to-case (RθJA) of 28.5°C/W, the estimated die junction temperature is approximately 16.4°C above ambient, or 101.4°C when TA = 85°C.