SNAS512K September   2011  – October 2025 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VCC and VCCO Power Supplies
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock Inputs
      2. 8.4.2 Clock Outputs
        1. 8.4.2.1 Reference Output
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Driving the Clock Inputs
        2. 9.2.1.2 Crystal Interface
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Termination and Use of Clock Drivers
          1. 9.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 9.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 9.2.2.1.3 Termination for Single-Ended Operation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Sequencing
      2. 9.3.2 Current Consumption and Power Dissipation Calculations
        1. 9.3.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
        2. 9.3.2.2 Power Dissipation Example #2: Worst-Case Dissipation
      3. 9.3.3 Power Supply Bypassing
        1. 9.3.3.1 Power Supply Ripple Rejection
      4. 9.3.4 Thermal Management
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.4 Thermal Information

THERMAL METRIC(1)(2)LMK00301UNIT
RHS0048A
(WQFN)
48 PINS
RθJAJunction-to-ambient thermal resistance28.5°C/W
RθJC(top) (DAP)Junction-to-case (top) thermal resistance7.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the package. Use the maximum number of vias in the board layout.