The LMK00301 has two universal inputs (CLKin0/CLKin0* and CLKin1/CLKin1*) that can accept AC-coupled or DC-coupled, 3.3V or 2.5V LVPECL, LVDS, CML, SSTL, and other differential and single-ended signals that meet the input requirements specified in Electrical Characteristics . The device can accept a wide range of signals due to the wide input common-mode voltage range (V_CM ) and input voltage swing (V_ID) / dynamic range. For 50% duty cycle and DC-balanced signals, AC coupling can also be employed to shift the input signal to within the V_CM range. Refer to Termination and Use of Clock Drivers for signal interfacing and termination techniques.

To achieve the best possible phase noise and jitter performance, the input must have a high slew rate of 3V/ns (differential) or higher. Driving the input with a lower slew rate degrades the noise floor and jitter. For this reason, TI recommends a differential signal input over a single-ended signal because this signal typically provides higher slew rate and common-mode-rejection. See the Noise Floor vs CLKin Slew Rate and RMS Jitter vs CLKin Slew Rate plots in Typical Characteristics section.

While TI recommends to drive the CLKin/CLKin* pair with a differential signal input, driving the pair with a single-ended clock is possible, provided the clock conforms to the Single-Ended Input specifications for CLKin pins listed in the Electrical Characteristics. For large single-ended input signals, such as 3.3V or 2.5V LVCMOS, place a 50Ω load resistor near the input for signal attenuation to prevent input overdrive as well as for line termination to minimize reflections. Again, the single-ended input slew rate must be as high as possible to minimize performance degradation. The CLKin input has an internal bias voltage of about 1.4V, so the input can be AC coupled as shown in Figure 9-2. The output impedance of the LVCMOS driver plus Rs must be close to 50Ω to match the characteristic impedance of the transmission line and load termination.

Figure 9-2 Single-Ended LVCMOS Input, AC Coupling

A single-ended clock can also be DC coupled to CLKinX as shown in Figure 9-3. Place a 50Ω load resistor near the CLKinX input for signal attenuation and line termination. Half of the single-ended swing of the driver (V_O,PP / 2) drives CLKinX, therefore CLKinX* must be externally biased to the midpoint voltage of the attenuated input swing ((V_O,PP / 2) × 0.5). The external bias voltage must be within the specified input common-mode voltage (V_CM) range. This can be achieved using external biasing resistors in the kΩ range (R_B1 and R_B2) or another low-noise voltage reference. This verifies that the input swing crosses the threshold voltage at a point where the input slew rate is the highest.

If the LVCMOS driver cannot achieve sufficient swing with a DC-terminated, 50Ω load at the CLKinX input as shown in Figure 9-3, then consider connecting the 50Ω load termination to ground through a capacitor (C_AC). This AC termination blocks the DC load current on the driver, so the voltage swing at the input is determined by the voltage divider formed by the source (Ro+Rs) and 50Ω load resistors. The value for C_AC depends on the trace delay, Td, of the 50Ω transmission line;

Figure 9-3 Single-Ended LVCMOS Input, DC Coupling With Common-Mode Biasing

If the crystal oscillator circuit is not used, driving the OSCin input with an single-ended external clock as shown in Figure 9-4 is possible. The input clock must be AC coupled to the OSCin pin, which has an internally-generated input bias voltage, and the OSCout pin must be left floating. While OSCin provides an alternative input to multiplex an external clock, TI recommends to use either universal input (CLKinX) because the inputs offer higher operating frequency, better common-mode and power supply noise rejection, and greater performance over supply voltage and temperature variations.

Figure 9-4 Driving OSCin With a Single-Ended Input