SNAS512K September   2011  – October 2025 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VCC and VCCO Power Supplies
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock Inputs
      2. 8.4.2 Clock Outputs
        1. 8.4.2.1 Reference Output
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Driving the Clock Inputs
        2. 9.2.1.2 Crystal Interface
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Termination and Use of Clock Drivers
          1. 9.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 9.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 9.2.2.1.3 Termination for Single-Ended Operation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Sequencing
      2. 9.3.2 Current Consumption and Power Dissipation Calculations
        1. 9.3.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
        2. 9.3.2.2 Power Dissipation Example #2: Worst-Case Dissipation
      3. 9.3.3 Power Supply Bypassing
        1. 9.3.3.1 Power Supply Ripple Rejection
      4. 9.3.4 Thermal Management
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.3.2.2 Power Dissipation Example #2: Worst-Case Dissipation

This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power dissipation. In this case, the maximum supply voltage and supply current values specified in Electrical Characteristics are used.

  • Maximum VCC = VCCO = 3.465V. Maximum ICC and ICCO values
  • CLKin0/CLKin0* input is selected
  • Banks A and B are configured for LVPECL: all outputs terminated with 50Ω to VT = VCCO – 2V
  • REFout is enabled with 5pF load
  • TA = 85°C

Using the maximum supply current and power calculations from the previous section, we can compute PTOTAL and PDEVICE.

  • From Equation 6: ICC_TOTAL = 10.5mA + 27mA + 27mA + 5.5mA = 70mA
  • From ICCO_PECL max spec: ICCO_BANK_A = ICCO_BANK_B = 197mA
  • From Equation 8: PTOTAL = 3.465V × (70mA + 197mA + 197mA + 10mA) = 1642.4mW
  • From Equation 9: PRT_PECL = ((2.57V – 1.47V)2/50Ω) + ((1.72V – 1.47V)2/50 Ω) = 25.5mW (per output pair)
  • From Equation 10: PVTT_PECL = 1.47V × [ ((2.57V – 1.47V) / 50Ω) + ((1.72V – 1.47V) / 50Ω) ] = 39.5mW (per output pair)
  • From Equation 11: PRT_HCSL = 0mW (no HCSL outputs)
  • From Equation 12: PDEVICE = 1642.4mW – (10 × (25.5mW + 39.5mW)) – 0mW = 992.4mW

In this worst-case example, the IC device dissipates approximately 992.4mW or 60% of the total power (1642.4mW), while the remaining 40% dissipates in the LVPECL emitter resistors (255mW for 10 pairs) and termination voltage (395mW into VCCO – 2V).

Based on θJA of 28.5°C/W, the estimated die junction temperature is about 28.3°C above ambient, or 113.3°C when TA = 85°C.