SNAU318 June   2025 LMX1205

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Additional Images
    2. 2.2 Jumper Information
    3. 2.3 Multiplier Lock Detect Jumper
    4. 2.4 Setup
      1. 2.4.1 Evaluation Setup Requirement
      2. 2.4.2 Connection Diagram
    5. 2.5 Power Requirements
    6. 2.6 Reference Clock
    7. 2.7 Output Connections
    8. 2.8 Test Points
  7. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
    3. 3.3 USB2ANY Interface
  8. 4Implementation Results
    1. 4.1 Buffer Mode
    2. 4.2 Multiplier and Divider Modes
    3. 4.3 Logic Clock
    4. 4.4 Programmable Delay
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Trademarks

4.2 Multiplier and Divider Modes

The LMX1205 contains a cascaded topology and facilitates the ability to adjust different multiply and divider values for custom frequencies within required operating frequency ranges.

Use the following steps to set the LMX1205 to divider mode:

  1. Select CLK_MUX = Divide.
  2. Select CLK_DIV to the appropriate divider value for respective CLKIN frequency.
LMX1205MSEVM Software Configuration for Divider Mode Figure 4-4 Software Configuration for Divider Mode

Use the following steps to set the LMX1205 to multiplier mode:

  1. Select CLK_MUX = Multiply.
  2. Select CLK_DIV to the appropriate multiplier value for respective CLKIN frequency.
  3. Select the Calibrate Multiplier button.
LMX1205MSEVM Software Configuration for Multiplier Mode Figure 4-5 Software Configuration for Multiplier Mode

In Figure 4-6, the primary device is set in multiplier mode (× 8), the secondary device is set in divider mode (÷ 4), and the reference clock to primary is 1GHz.

LMX1205MSEVM Phase Noise Plots for Multiplier Mode (× 8), 1GHz Reference, and (÷ 4) Divider Mode Figure 4-6 Phase Noise Plots for Multiplier Mode (× 8), 1GHz Reference, and (÷ 4) Divider Mode

In Figure 4-7, the primary device is set in divider mode (÷ 3), the secondary device is set in multiplier mode (× 7), and the reference clock to primary is 3GHz.

LMX1205MSEVM Phase Noise Plots for Reference at 3GHz, (÷ 3) Divider mode, and Multiplier Mode (× 7) Figure 4-7 Phase Noise Plots for Reference at 3GHz, (÷ 3) Divider mode, and Multiplier Mode (× 7)

Figure 4-6 and Figure 4-7 demonstrate that the LMX1205 synthesizes any frequency in a cascaded clock tree using multiplier and divider modes. The LMX1205 complies with the operating range of frequencies for the device.