SNAU318 June   2025 LMX1205

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Additional Images
    2. 2.2 Jumper Information
    3. 2.3 Multiplier Lock Detect Jumper
    4. 2.4 Setup
      1. 2.4.1 Evaluation Setup Requirement
      2. 2.4.2 Connection Diagram
    5. 2.5 Power Requirements
    6. 2.6 Reference Clock
    7. 2.7 Output Connections
    8. 2.8 Test Points
  7. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
    3. 3.3 USB2ANY Interface
  8. 4Implementation Results
    1. 4.1 Buffer Mode
    2. 4.2 Multiplier and Divider Modes
    3. 4.3 Logic Clock
    4. 4.4 Programmable Delay
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Trademarks

1.1 Introduction

The LMX1205 is an ultra-low additive-jitter RF buffer, divider, and multiplier, with integrated SYSREF generation capability. Use a separate auxiliary clock divider with large divider values called logic clock for FPGAs or other logic ICs. Each RF output is paired with a differential SYSREF output with picosecond-precision delay-tuning capability and is operable as a generator (with synchronization capability across multiple devices) or as a repeater. The EVM operates with a 3.3V supply voltage when the onboard low dropout (LDO) regulators are used. When the supply voltage is 2.5V, LDO bypass is possible. The EVM contains three LMX1205, three LDO regulators, and a vertical header connector for the USB2ANY connection.