SNAU318 June   2025 LMX1205

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Additional Images
    2. 2.2 Jumper Information
    3. 2.3 Multiplier Lock Detect Jumper
    4. 2.4 Setup
      1. 2.4.1 Evaluation Setup Requirement
      2. 2.4.2 Connection Diagram
    5. 2.5 Power Requirements
    6. 2.6 Reference Clock
    7. 2.7 Output Connections
    8. 2.8 Test Points
  7. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
    3. 3.3 USB2ANY Interface
  8. 4Implementation Results
    1. 4.1 Buffer Mode
    2. 4.2 Multiplier and Divider Modes
    3. 4.3 Logic Clock
    4. 4.4 Programmable Delay
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Trademarks

2.7 Output Connections

Only selected CLKOUT, SYSREFOUT, LOGICLKOUT channels are exposed from primary and secondary device.

Table 2-1 Clock and SYSREF Signals for Primary and Secondary Devices
SITE OUTPUTS COMMENTS
PRIMARY CLKOUT0 TERMINATED
CLKOUT1 INPUT TO SECONDARY 1
CLKOUT2 EDGE SMA
CLKOUT3 INPUT TO SECONDARY 2
SYSREFOUT0 TERMINATED
SYSREFOUT1 INPUT TO SECONDARY 1
SYSREFOUT2 EDGE SMA
SYSREFOUT3 INPUT TO SECONDARY 2
LOGICLK VERTICAL SMP
LOGISYSREF TERMINATED
SECONDARY 1 CLKOUT0 TERMINATED
CLKOUT1 VERTICAL SMA
CLKOUT2 EDGE SMA
CLKOUT3 TERMINATED
SYSREFOUT0 TERMINATED
SYSREFOUT1 EDGE SMA
SYSREFOUT2 EDGE SMA
SYSREFOUT3 TERMINATED
LOGICLK VERTICAL SMP
LOGISYSREF TERMINATED
SECONDARY 2 CLKOUT0 TERMINATED
CLKOUT1 EDGE SMA
CLKOUT2 VERTICAL SMA
CLKOUT3 TERMINATED
SYSREFOUT0 TERMINATED
SYSREFOUT1 EDGE SMA
SYSREFOUT2 EDGE SMA
SYSREFOUT3 TERMINATED
LOGICLK VERTICAL SMP
LOGISYSREF TERMINATED

TERMINATED – terminated differentially on board with a 100ohm resistor, the clock path is not measurable.

All exposed output connections are AC-coupled with wideband caps and connect directly to RF instruments. An additional DC block is not required for the connection. Terminate the unused CLKOUT SMA connector with a 50Ω load. If a balun with the best frequency range is available, use a differential connection. Because LOGICCLK outputs are also AC-coupled, only LVDS output formats have been evaluated.