SNAU318 June   2025 LMX1205

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Additional Images
    2. 2.2 Jumper Information
    3. 2.3 Multiplier Lock Detect Jumper
    4. 2.4 Setup
      1. 2.4.1 Evaluation Setup Requirement
      2. 2.4.2 Connection Diagram
    5. 2.5 Power Requirements
    6. 2.6 Reference Clock
    7. 2.7 Output Connections
    8. 2.8 Test Points
  7. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
    3. 3.3 USB2ANY Interface
  8. 4Implementation Results
    1. 4.1 Buffer Mode
    2. 4.2 Multiplier and Divider Modes
    3. 4.3 Logic Clock
    4. 4.4 Programmable Delay
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Trademarks

4.3 Logic Clock

LMX1205MSEVM PCB shows that the logic clock is enabled by default in the LVDS output format.

LMX1205MSEVM Software Configuration to select Logic Clock Figure 4-8 Software Configuration to select Logic Clock

Figure 4-9 shows an input clock frequency of 2GHz. The dividers operate in default settings to generate 31.25MHz at the logic clock output.

LMX1205MSEVM Output Waveform of Logic Clock Figure 4-9 Output Waveform of Logic Clock