SNAU318 June   2025 LMX1205

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Additional Images
    2. 2.2 Jumper Information
    3. 2.3 Multiplier Lock Detect Jumper
    4. 2.4 Setup
      1. 2.4.1 Evaluation Setup Requirement
      2. 2.4.2 Connection Diagram
    5. 2.5 Power Requirements
    6. 2.6 Reference Clock
    7. 2.7 Output Connections
    8. 2.8 Test Points
  7. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
    3. 3.3 USB2ANY Interface
  8. 4Implementation Results
    1. 4.1 Buffer Mode
    2. 4.2 Multiplier and Divider Modes
    3. 4.3 Logic Clock
    4. 4.4 Programmable Delay
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Trademarks

5.1 Schematics

LMX1205MSEVM LMX1205 Multisite EVM Schematic Figure 5-1 LMX1205 Multisite EVM Schematic
LMX1205MSEVM Main Device Schematic for Primary and Secondary Figure 5-2 Main Device Schematic for Primary and Secondary
LMX1205MSEVM SPI Lines Figure 5-3 SPI Lines
LMX1205MSEVM Device Supply LDO Figure 5-4 Device Supply LDO
LMX1205MSEVM Logic Clock SMP Output Figure 5-5 Logic Clock SMP Output
LMX1205MSEVM Vertical SMA for Secondary Device Figure 5-6 Vertical SMA for Secondary Device
LMX1205MSEVM Edge SMA for all Devices Figure 5-7 Edge SMA for all Devices