SNIS237A December   2024  – April 2025 TMP118

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Two-Wire Interface Timing
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 Averaging
      3. 7.3.3 Temperature Comparator and Hysteresis
      4. 7.3.4 Strain Tolerance
      5. 7.3.5 NIST Traceability
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conversion Mode
      2. 7.4.2 One-Shot Mode (OS)
    5. 7.5 Programming
      1. 7.5.1 I2C and SMBus Interface
        1. 7.5.1.1 Serial Interface
          1. 7.5.1.1.1 Bus Overview
          2. 7.5.1.1.2 Device Address
          3. 7.5.1.1.3 Writing and Reading Operation
            1. 7.5.1.1.3.1 Writes
            2. 7.5.1.1.3.2 Reads
          4. 7.5.1.1.4 General-Call Reset Function
          5. 7.5.1.1.5 Timeout Function
          6. 7.5.1.1.6 Coexistence on I3C Mixed Bus
  9. 8 Device Registers
    1. 8.1 Register Map
      1. 8.1.1 Temp_Result Register (address = 00h) [reset = 0000h]
      2. 8.1.2 Configuration Register (address = 01h) [reset = 60B0h]
      3. 8.1.3 TLow_Limit Register (address = 02h) [reset = 2580h]
      4. 8.1.4 THigh_Limit Register (address = 03h) [reset = 2800h]
      5. 8.1.5 Device ID Register (Address = 0Bh) [reset = 1180h]
      6. 8.1.6 Unique_ID0 Register (Address = 0Ch) [reset = xxxxh]
      7. 8.1.7 Unique_ID1 Register (Address = 0Dh) [reset = xxxxh]
      8. 8.1.8 Unique_ID2 Register (Address = 0Eh) [reset = xxxxh]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Separate I2C Pullup and Supply Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Equal I2C Pullup and Supply Voltage Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
7.5.1.1.2 Device Address

To communicate with the TMP118 the controller must first address target devices through an address byte. The address byte has seven address bits and a read-write (R/W) bit that indicates the intent of executing a read or write operation. The TMP118 utilizes hardwired orderables for addressing to allow up to 4 target devices to be addressed on a single bus.

Table 7-4 Device Address Options
7-BIT I2C TARGET ADDRESS

DEVICE

HEX

BINARY

TMP118A/ TMP118MA

0x48

1001000'b

TMP118B/ TMP118MB

0x49

1001001'b

TMP118C/ TMP118MC

0x4A

1001010'b

TMP118D/ TMP118MD

0x4B

1001011'b