SNLA239D May 2021 – April 2025 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS , DP83869HM
Configure PHY to output Test Mode 4 by setting MDIO registers according to 1000 Base Test Mode 4 in Appendix B.
Figure 2-6 IEEE Test Mode 4
per Standard