SNLA452 August   2025 DP83TD510E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Component Checklist
    3. 2.3 Device Health Checks
      1. 2.3.1 Check Voltage Supply Pins
      2. 2.3.2 Probe the RST_N Pin
      3. 2.3.3 Probe the CLKOUT Pin
      4. 2.3.4 Probe the SMI Pins
    4. 2.4 Read and Check Register Values
    5. 2.5 Verifying Strap Configuration
    6. 2.6 Loopbacks
    7. 2.7 MDI Health Checks
      1. 2.7.1 Link Up Common Issues
      2. 2.7.2 Transmit Level
        1. 2.7.2.1 Change Transmit Level
      3. 2.7.3 Time-Domain Reflectometry
      4. 2.7.4 Signal Quality Check
      5. 2.7.5 MDI Test Modes
    8. 2.8 MII Health Checks
      1. 2.8.1 RGMII
      2. 2.8.2 RMII
      3. 2.8.3 MII
  6. 3Summary
  7. 4References

2.8.1 RGMII

The RGMII interface can be chosen via straps or by using register 0x17. Failing to meet the timing requirements listed in the data sheet for RGMII is a common issue. While the RGMII interface has the strictest timing requirements amoung the interface options, these requirements are not as strict for 10Mbps speeds as compared to gigabit RGMII. Regardless, it's crucial to verify that the timing requirements are being met. These requirements are listed in section 5.6 of the data sheet.

Also verify that the required signals for RGMII shown below are all routed properly between the PHY and the MAC.

If a MAC bus is suspected to be problematic, probe the lines at the receiver side of the trace making sure that the receiver's setup an hold times are met, along with VIH/VIL. Typical symptoms of violating these specifications is packet errors at the MAC while the PHY is indicating clean traffic (Register 0x15)

RGMII clock shift can be toggled using register 0x0017 bits [12:11] to meet these requirements

RGMII SignalingFigure 2-9 RGMII Signaling