SNLA452 August   2025 DP83TD510E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Component Checklist
    3. 2.3 Device Health Checks
      1. 2.3.1 Check Voltage Supply Pins
      2. 2.3.2 Probe the RST_N Pin
      3. 2.3.3 Probe the CLKOUT Pin
      4. 2.3.4 Probe the SMI Pins
    4. 2.4 Read and Check Register Values
    5. 2.5 Verifying Strap Configuration
    6. 2.6 Loopbacks
    7. 2.7 MDI Health Checks
      1. 2.7.1 Link Up Common Issues
      2. 2.7.2 Transmit Level
        1. 2.7.2.1 Change Transmit Level
      3. 2.7.3 Time-Domain Reflectometry
      4. 2.7.4 Signal Quality Check
      5. 2.7.5 MDI Test Modes
    8. 2.8 MII Health Checks
      1. 2.8.1 RGMII
      2. 2.8.2 RMII
      3. 2.8.3 MII
  6. 3Summary
  7. 4References

2.8.2 RMII

The RMII interface can be chosen via straps or by using register 0x17. Similarly to RGMII and MII, RMII also has certain timing requirements that must be met for proper function of the PHY. These requirements are listed in section 5.6 of the data sheet.

Unlike RGMII and MII, RMII has master and slave modes. These modes can be strapped to on power-up and cannot be changed through registers.

If a MAC bus is suspected to be problematic, probe the lines at the receiver side of the trace making sure that the receiver's setup an hold times are met, along with VIH/VIL. Typical symptoms of violating these specifications is packet errors at the MAC while the PHY is indicating clean traffic (Register 0x15)

RMII clock shift can be toggled using register 0x0017 bit [8] to meet these requirements

In RMII Master mode, the DP83TD510 operates off of the 25MHz input clock (crystal or oscillator) and supplies the MAC with a referenced 50MHz clock to synchronize the data. This clock can be shifted to make sure that the setup and hold times for the receiver (MAC) is met by using register 0x17 [9]. Enabling this delay adds approximately 4ns Delay on the 50MHz output clock. The setup and hold times are an important timing requirement and must be met to make sure that no packet loss or errors occur during transmission.

RMII Master SignalingFigure 2-10 RMII Master Signaling
RMII Clock Shift DisabledFigure 2-11 RMII Clock Shift Disabled
RMII Clock Shift EnabledFigure 2-12 RMII Clock Shift Enabled

In RMII Slave mode, the DP83TD510 operates off a 50MHz input clock which is shared by both the PHY and the MAC. Alternatively, the PHY can operate off a 50MHz reference clock provided by the MAC. Make sure that this clock being supplied to the PHY in RMII Slave mode meets the requirement for ± 100ppm for proper functioning of the PHY.

RMII Slave SignalingFigure 2-13 RMII Slave Signaling

Since each mode requires a different input clock signal, make sure that the correct or expected RMII mode is being strapped during power-up for the device to boot up and perform properly.