SNLA452 August   2025 DP83TD510E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Component Checklist
    3. 2.3 Device Health Checks
      1. 2.3.1 Check Voltage Supply Pins
      2. 2.3.2 Probe the RST_N Pin
      3. 2.3.3 Probe the CLKOUT Pin
      4. 2.3.4 Probe the SMI Pins
    4. 2.4 Read and Check Register Values
    5. 2.5 Verifying Strap Configuration
    6. 2.6 Loopbacks
    7. 2.7 MDI Health Checks
      1. 2.7.1 Link Up Common Issues
      2. 2.7.2 Transmit Level
        1. 2.7.2.1 Change Transmit Level
      3. 2.7.3 Time-Domain Reflectometry
      4. 2.7.4 Signal Quality Check
      5. 2.7.5 MDI Test Modes
    8. 2.8 MII Health Checks
      1. 2.8.1 RGMII
      2. 2.8.2 RMII
      3. 2.8.3 MII
  6. 3Summary
  7. 4References

1 Introduction

DP83TD510E is a physical-layer transceiver compliant to IEEE 802.3cg 10Base-T1L specification. The PHY uses low noise coupled signal processing receiver architecture to offer longer cable reach along with ultra-low power consumption. The device supports both 2.4V p2p and 1V p2p voltage modes as defined by IEEE 802.3cg 10Base-T1L specifications. DP83TD510E supports direct connection to several Media Access Controller (MAC) interfaces (MII, RMII, RGMII, and low power RMII). The device also supports back-to-back RMII mode and RGMII in non-managed mode to provide range extension and repeater functionality.

Figure 1-1 shows a high-level overview of a typical media conversion application (SPE ↔ RJ-45) with DP83TD510E:


DP83TD510E-EVM Block Diagram
Figure 1-1 DP83TD510E-EVM Block Diagram