SNLA452 August   2025 DP83TD510E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Component Checklist
    3. 2.3 Device Health Checks
      1. 2.3.1 Check Voltage Supply Pins
      2. 2.3.2 Probe the RST_N Pin
      3. 2.3.3 Probe the CLKOUT Pin
      4. 2.3.4 Probe the SMI Pins
    4. 2.4 Read and Check Register Values
    5. 2.5 Verifying Strap Configuration
    6. 2.6 Loopbacks
    7. 2.7 MDI Health Checks
      1. 2.7.1 Link Up Common Issues
      2. 2.7.2 Transmit Level
        1. 2.7.2.1 Change Transmit Level
      3. 2.7.3 Time-Domain Reflectometry
      4. 2.7.4 Signal Quality Check
      5. 2.7.5 MDI Test Modes
    8. 2.8 MII Health Checks
      1. 2.8.1 RGMII
      2. 2.8.2 RMII
      3. 2.8.3 MII
  6. 3Summary
  7. 4References

2.6 Loopbacks

The DP83TD510E has several loopback options that enable verification of various functional blocks within the PHY. A block diagram of the different loopback modes offered by the PHY is shown in Figure 2-3.

Loopback Block DiagramFigure 2-3 Loopback Block Diagram

MII Loopback can be configured through the Control Register (BMCR, address 0x0000). All other loopback modes are enabled using the BIST Control Register (BISCR, address 0x0016). These loopback modes can be used to validate both the MII, MDI, and the internal blocks within the PHY. This can be crucial in narrowing down the part of the data path responsible for behavior such as packet loss/errors.

Table 2-3 shows the register writes to enable each loopback mode, assuming the other register configurations are left as default.

Table 2-3 Register Writes for Loopbacks
Loopback ModeRegisterWrite Value
MII Loopback0x00000x4000
PCS Loopback0x00160x0102
Digital Loopback0x00160x0104
Analog Loopback0x00160x0108
Reverse Loopback0x00160x0110

There are a few built in counters, for both TX and RX, that can aid in debugging with loopbacks. The counters can be used to validate the number of packets being received or transmitted in different loopback modes. Note that the counters are reset if 0x12B, 0x12C, and 0x12D for TX counters, and 0x12E, 0x12F, and 0x130 for RX counters. These counters can be found in the set of registers given in Table 2-4.

Table 2-4 TX/RX Packet Counter Registers
RegisterFunction
0x012A

[1] RX CRC Indication

[0] TX CRC Indication

0x012BLower 16 bits TX Packet Counter
0x012CUpper 16 bits TX Packet Counter
0x012DTX Packets with CRC Errors
0x012ELower 16 bits RX Packet Counter
0x012FUpper 16 bits RX Packet Counter
0x0130RX Packets with CRC Errors