SNLA452 August   2025 DP83TD510E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Component Checklist
    3. 2.3 Device Health Checks
      1. 2.3.1 Check Voltage Supply Pins
      2. 2.3.2 Probe the RST_N Pin
      3. 2.3.3 Probe the CLKOUT Pin
      4. 2.3.4 Probe the SMI Pins
    4. 2.4 Read and Check Register Values
    5. 2.5 Verifying Strap Configuration
    6. 2.6 Loopbacks
    7. 2.7 MDI Health Checks
      1. 2.7.1 Link Up Common Issues
      2. 2.7.2 Transmit Level
        1. 2.7.2.1 Change Transmit Level
      3. 2.7.3 Time-Domain Reflectometry
      4. 2.7.4 Signal Quality Check
      5. 2.7.5 MDI Test Modes
    8. 2.8 MII Health Checks
      1. 2.8.1 RGMII
      2. 2.8.2 RMII
      3. 2.8.3 MII
  6. 3Summary
  7. 4References

2.5 Verifying Strap Configuration

Incorrect strap configurations are one of the most common issues leading to lack of data throughput. For example, if the incorrect MII interface is chosen, or an incorrect PHY address is strapped, data transmission cannot be successful.

Make sure that the MAC is not driving any pins connected to the PHY during power-up or reset pin de-assertion. This can cause an incorrect voltage to be sampled during this time, and cause the strap value to change, because of which the device can perform stochastically. All MAC pins connected to the PHY must be placed in a High-Z state while the PHY is powering up or being coming out of reset.

Strap values sampled at power-up can be read from the register 0x467 (CHIP_SOR_1) using Extended Register Access. More information about strapping is given in section 6.4.1 of the data sheet.