SNLS779 Data sheet

SNLS779A July 2025 – November 2025 DP83TC815-Q1

PRODUCTION DATA

8.2 DP83TC815 Registers

Table 8-3 lists the memory-mapped registers for the DP83TC815 registers. All register offset addresses not listed in Table 8-3 must be considered as reserved locations and the register contents must not be modified.

Table 8-3 DP83TC815 Registers

Offset	Acronym	Register Name	Section
0h	BMCR	IEEE Control Register	Section 8.2.1
1h	BMSR	IEEE Status Register	Section 8.2.2
2h	PHYIDR1	PHY Identification Register - 1	Section 8.2.3
3h	PHYIDR2	PHY Identification Register - 2	Section 8.2.4
10h	PHYSTS	PHY Status Register	Section 8.2.5
11h	PHYSCR	Software Control Register	Section 8.2.6
12h	MISR1	Interrupt Register -1	Section 8.2.7
13h	MISR2	Interrupt Register -2	Section 8.2.8
15h	RECR	RX Error Count Register	Section 8.2.9
16h	BISCR	BIST Control Register	Section 8.2.10
17h	MISR4	Interrupt Register -4	Section 8.2.11
18h	MISR3	Interrupt Register -3	Section 8.2.12
19h	REG_19	PHY Address Status Register	Section 8.2.13
1Ah	REG_1A	Receive Symbol Status Register	Section 8.2.14
1Bh	TC10_ABORT_REG	TC10 Abort Register	Section 8.2.15
1Eh	CDCR	TDR Run Status Register	Section 8.2.16
1Fh	PHYRCR	Reset Control Register	Section 8.2.17
3Eh	Register_3E	Register_3E	Section 8.2.18
133h	Register_133	CnS Status Register	Section 8.2.19
17Fh	Register_17F	WUR WUP Configuration Register	Section 8.2.20
181h	Register_181	LPS Received Count Register	Section 8.2.21
182h	Register_182	WUR Received Count Register	Section 8.2.22
184h	LPS_CFG	Low Power Configuration Register - 0	Section 8.2.23
18Bh	LPS_CFG2	Low Power Configuration Register - 2	Section 8.2.24
18Ch	LPS_CFG3	Low Power Configuration Register - 3	Section 8.2.25
18Dh	LINK_FAIL_CNT	Link Fail Count Register	Section 8.2.26
18Eh	LPS_STATUS	Low Power Status Register	Section 8.2.27
1A0h	PCF	PHY Control Frame Configuration Register	Section 8.2.28
1A2h	MISC1	SA DA Configuration Register	Section 8.2.29
1A3h	PPM0	PPM Monitor Config Register - 0	Section 8.2.30
1A4h	PPM1	PPM Monitor Config Register - 1	Section 8.2.31
1A5h	PPM2	PPM Monitor Config Register - 2	Section 8.2.32
1A6h	PPM3	PPM Monitor Config Register - 3	Section 8.2.33
1A7h	PPM4	PPM Monitor Config Register - 4	Section 8.2.34
1A8h	PPM5	PPM Monitor Config Register - 5	Section 8.2.35
1A9h	PPM6	PPM Monitor Config Register - 6	Section 8.2.36
1AAh	PPM7	PPM Monitor Config Register - 7	Section 8.2.37
1ADh	PPM10	PPM Monitor Config Register - 10	Section 8.2.38
1AEh	PPM11	PPM Monitor Config Register - 11	Section 8.2.39
1AFh	PPM12	PPM Monitor Config Register - 12	Section 8.2.40
1BEh	fwu_reg_3	Fast Wake Up Register - 3	Section 8.2.41
1D2h	spare_reg_tc10	Fast Wake Up Spare Register	Section 8.2.42
310h	TDR_TC1	TDR Status Register	Section 8.2.43
402h	ANA_LD_CTRL_3	VDDIO Level Status Register	Section 8.2.44
430h	A2D_REG_48	RGMII ID Control Register	Section 8.2.45
440h	A2D_REG_64	ESD Event Count Register - 0	Section 8.2.46
442h	A2D_REG_66	ESD Event Count Register - 1	Section 8.2.47
444h	A2D_REG_68	TC10 Force Control Register	Section 8.2.48
450h	LEDS_CFG_1	LED Configuration Register - 1	Section 8.2.49
451h	LEDS_CFG_2	LED Configuration Register - 2	Section 8.2.50
452h	IO_MUX_CFG_1	IO Multiplexing Register - 1	Section 8.2.51
453h	IO_MUX_CFG_2	IO Multiplexing Register - 2	Section 8.2.52
455h	IO_CONTROL_2	IO Control Register - 2	Section 8.2.53
456h	IO_MUX_CFG	xMII Impedance Control Register	Section 8.2.54
45Dh	CHIP_SOR_1	Strap Status Register	Section 8.2.55
45Fh	LED1_CLKOUT_ANA_CTRL	CLKOUT and LED_1 Control Register	Section 8.2.56
460h	IMPEDANCE_CTRL_0	Impedance Control Register - 0	Section 8.2.57
461h	IMPEDANCE_CTRL_1	Impedance Control Register - 1	Section 8.2.58
4DFh	RX_FIFO_CONFIG	RX_FIFO_CONFIG	Section 8.2.59
4EEh	LINKUP_TIMER_1	Link Up Timer Register - 1	Section 8.2.60
4EFh	LINKUP_TIMER_2	Link Up Timer Register - 2	Section 8.2.61
523h	TX_PR_FILT_CTRL	MDI Transmit Force Register	Section 8.2.62
551h	PG_REG_1	CRS_DV Control Register	Section 8.2.63
552h	PG_REG_3	PG_REG_3	Section 8.2.64
553h	PG_REG_4	Auto-Polarity Correction Control Register	Section 8.2.65
561h	TC1_LINK_FAIL_LOSS	TC1 Link Fail Count Register	Section 8.2.66
562h	TC1_LINK_TRAINING_TIME	TC1 Link Training Time Register	Section 8.2.67
563h	NO_LINK_TH	No Link Interrupt TimeThreshold Register	Section 8.2.68
5A0h	DITH_CTRL_0	Dithering Control Register - 0	Section 8.2.69
5A1h	DITH_CTRL_1	Dithering Control Register - 1	Section 8.2.70
5A8h	DITH_RFI_EN_CTRL	Dithering Enable Register	Section 8.2.71
5B2h	CFG_PCF_DMAC_ADDR	Configurable Last Two Bytes of PCF DMAC	Section 8.2.72
5B7h	SPARE_IN_FROM_DIG_SL_1	Register With Configurable Bits For Analog	Section 8.2.73
5B8h	CONTROL_REG_1	Dithering Disable Control	Section 8.2.74
600h	RGMII_CTRL	RGMII Control Register	Section 8.2.75
601h	RGMII_FIFO_STATUS	RGMII FIFO Status Register	Section 8.2.76
602h	RGMII_CLK_SHIFT_CTRL	RGMII Shift Control Register	Section 8.2.77
608h	SGMII_CTRL_1	SGMII Control Register - 1	Section 8.2.78
60Ah	SGMII_STATUS	SGMII Status Register	Section 8.2.79
60Ch	SGMII_CTRL_2	SGMII Control Register - 2	Section 8.2.80
60Dh	SGMII_FIFO_STATUS	SGMII FIFO Status Register	Section 8.2.81
618h	PRBS_STATUS_1	PRBS Status Register - 1	Section 8.2.82
619h	PRBS_CTRL_1	PRBS Control Register - 1	Section 8.2.83
61Ah	PRBS_CTRL_2	PRBS Control Register - 2	Section 8.2.84
61Bh	PRBS_CTRL_3	PRBS Control Register - 3	Section 8.2.85
61Ch	PRBS_STATUS_2	PRBS Status Register - 2	Section 8.2.86
61Dh	PRBS_STATUS_3	PRBS Status Register - 3	Section 8.2.87
61Eh	PRBS_STATUS_4	PRBS Status Register - 4	Section 8.2.88
620h	PRBS_STATUS_5	PRBS Status Register - 5	Section 8.2.89
622h	PRBS_STATUS_6	PRBS Status Register - 6	Section 8.2.90
623h	PRBS_STATUS_7	PRBS Status Register - 7	Section 8.2.91
624h	PRBS_CTRL_4	PRBS Control Register - 4	Section 8.2.92
625h	PATTERN_CTRL_1	BIST Pattern Control Register - 1	Section 8.2.93
626h	PATTERN_CTRL_2	BIST Pattern Control Register - 2	Section 8.2.94
627h	PATTERN_CTRL_3	BIST Pattern Control Register - 3	Section 8.2.95
628h	PMATCH_CTRL_1	BIST Match Control Register - 1	Section 8.2.96
629h	PMATCH_CTRL_2	BIST Match Control Register - 2	Section 8.2.97
62Ah	PMATCH_CTRL_3	BIST Match Control Register - 3	Section 8.2.98
638h	PKT_CRC_STAT	BIST CRC Status Register	Section 8.2.99
639h	TX_PKT_CNT_1	xMII TX Packet Count Register - 1	Section 8.2.100
63Ah	TX_PKT_CNT_2	xMII TX Packet Count Register - 2	Section 8.2.101
63Bh	TX_PKT_CNT_3	xMII TX Packet Count Register - 3	Section 8.2.102
63Ch	RX_PKT_CNT_1	xMII RX Packet Count Register - 1	Section 8.2.103
63Dh	RX_PKT_CNT_2	xMII RX Packet Count Register - 2	Section 8.2.104
63Eh	RX_PKT_CNT_3	xMII RX Packet Count Register - 3	Section 8.2.105
648h	RMII_CTRL_1	RMII Control Register	Section 8.2.106
649h	RMII_STATUS_1	RMII FIFO Status Register	Section 8.2.107
D00h	PTP_CTL	PTP Control Register	Section 8.2.108
D01h	PTP_TDR	PTP Time Data Register	Section 8.2.109
D02h	PTP_STS	PTP Status Register	Section 8.2.110
D03h	PTP_TSTS	PTP Trigger Status Register	Section 8.2.111
D04h	PTP_RATEL	PTP Rate Low Register	Section 8.2.112
D05h	PTP_RATEH	PTP Rate High Register	Section 8.2.113
D08h	PTP_TXTS	PTP Transmit Timestamp Register	Section 8.2.114
D09h	PTP_RXTS	PTP Receive Timestamp Register	Section 8.2.115
D0Ah	PTP_ESTS	PTP Event Status Register	Section 8.2.116
D10h	PTP_TRIG	PTP Trigger Configuration Register	Section 8.2.117
D11h	PTP_EVNT	PTP Event Configuration Register	Section 8.2.118
D12h	PTP_TXCFG0	PTP Transmit Configuration Register 0	Section 8.2.119
D13h	PTP_TXCFG1	PTP Transmit Configuration Register 1	Section 8.2.120
D14h	PSF_CFG0	PHY Status Frame Configuration Register 0	Section 8.2.121
D15h	PTP_RXCFG0	PTP Receive Configuration Register 0	Section 8.2.122
D16h	PTP_RXCFG1	PTP Receive Configuration Register 1	Section 8.2.123
D17h	PTP_RXCFG2	PTP Receive Configuration Register 2	Section 8.2.124
D18h	PTP_RXCFG3	PTP Receive Configuration Register 3	Section 8.2.125
D19h	PTP_RXCFG4	PTP Receive Configuration Register 4	Section 8.2.126
D1Ah	PTP_TRDL	PTP Temporary Rate Duration Low Register	Section 8.2.127
D1Bh	PTP_TRDH	PTP Temporary Rate Duration High Register	Section 8.2.128
D1Ch	PTP_EVNT_TSU_CFG	Event Timestamp Storage Configuration	Section 8.2.129
D1Dh	PSF_TRIG_TS_EN	Trigger Timestamp PHY Status Frame Enable	Section 8.2.130
D20h	PTP_COC	PTP Clock Output Control Register	Section 8.2.131
D21h	PSF_CFG1	Phy Status Frame Configuration Register 1	Section 8.2.132
D22h	PSF_CFG2	Phy Status Frame Configuration Register 2	Section 8.2.133
D23h	PSF_CFG3	Phy Status Frame Configuration Register 3	Section 8.2.134
D24h	PSF_CFG4	Phy Status Frame Configuration Register 4	Section 8.2.135
D26h	PTP_INTCTL	PTP Interrupt Control Register	Section 8.2.136
D27h	PTP_CLKSRC	PTP Clock Source Register	Section 8.2.137
D28h	PTP_ETYPE	PTP Ethernet Type Register	Section 8.2.138
D29h	PTP_OFF	PTP Offset Register	Section 8.2.139
D2Bh	PTP_RXHASH	PTP Receive Hash Register	Section 8.2.140
D30h	PTP_EVENT_GPIO_SEL	PTP Event GPIO selection	Section 8.2.141
D32h	TX_SMD_GPIO_CTL	TX path SMD detection and GPIO control	Section 8.2.142
D33h	SCH_CTL_1	Scheduler control 1	Section 8.2.143
D34h	SCH_CTL_2	Scheduler control 2	Section 8.2.144
D35h	FREQ_CTL_1	Base frequency control 1	Section 8.2.145
D36h	FREQ_CTL_2	Base frequency control 2	Section 8.2.146
D37h	PTP_RATEL_ACC_ONLY	PTP Rate ACC only LSB Register	Section 8.2.147
D38h	PTP_RATEH_ACC_ONLY	PTP Rate ACC only MSB Register and enable	Section 8.2.148
D39h	PTP_PLL_CTL	PTP_PLL control register	Section 8.2.149
D3Ah	PTP_PLL_RD_1	PTP timestamp read register 1	Section 8.2.150
D3Bh	PTP_PLL_RD_2	PTP timestamp read register 2	Section 8.2.151
D3Ch	PTP_PLL_RD_3	PTP timestamp read register 3	Section 8.2.152
D3Dh	PTP_PLL_RD_4	PTP timestamp read register 4	Section 8.2.153
D3Eh	PTP_PLL_RD_5	PTP timestamp read register 5	Section 8.2.154
D3Fh	PTP_PLL_RD_6	PTP timestamp read register 6	Section 8.2.155
D40h	PTP_ONESTEP_OFF	PTP ONESTEP OFFSET register	Section 8.2.156
D45h	PTP_PSF_VLAN_CFG_1	PSF VLAN Configuration 1	Section 8.2.157
D46h	PTP_PSF_VLAN_CFG_2	PSF VLAN Configuration 2	Section 8.2.158
D47h	PTP_PSF_VLAN_CFG_3	PSF VLAN Configuration 3	Section 8.2.159
D48h	MAX_IPV4_LENGTH	PSF IPv4 Packet Length	Section 8.2.160
D49h	PTP_TXCFG_2	PTP Domain Filter Controls	Section 8.2.161
D4Ah	PSF_DMAC_1	PSF DMAC Address 1	Section 8.2.162
D4Bh	PSF_DMAC_2	PSF DMAC Address 2	Section 8.2.163
D4Ch	PSF_DMAC_3	PSF DMAC Address 3	Section 8.2.164
D4Dh	PSF_SMAC_1	PSF SMAC Address 1	Section 8.2.165
D4Eh	PSF_SMAC_2	PSF SMAC Address 2	Section 8.2.166
D4Fh	PSF_SMAC_3	PSF SMAC Address 3	Section 8.2.167
D50h	PSF_ETYPE	PSF Ether Type	Section 8.2.168
D51h	IPV4_DA_1	PSF Destination Address 1	Section 8.2.169
D52h	IPV4_DA_2	PSF Destination Address 2	Section 8.2.170
D53h	PSF_SOURCE_UDP_PORT	PSF UDP Source Port Address	Section 8.2.171
D54h	PSF_DESTINATION_UDP_PORT	PSF UDP Destination Port Address	Section 8.2.172
DE0h	PTP_LAT_COMP_CTRL	PTP Latency Compensation Control	Section 8.2.173
DF0h	PTP_DEBUG_SEL	PTP Debug Select	Section 8.2.174
1000h	MMD1_PMA_CTRL_1	PMA Control 1	Section 8.2.175
1001h	MMD1_PMA_STATUS_1	PMA Status 1	Section 8.2.176
1007h	MMD1_PMA_STAUS_2	PMA Status 2	Section 8.2.177
100Bh	MMD1_PMA_EXT_ABILITY_1	PMA Extended 1	Section 8.2.178
1012h	MMD1_PMA_EXT_ABILITY_2	PMA Extended 2	Section 8.2.179
1834h	MMD1_PMA_CTRL_2	PMA Control 2	Section 8.2.180
1836h	MMD1_PMA_TEST_MODE_CTRL	PMA Test	Section 8.2.181
3000h	MMD3_PCS_CTRL_1	PCS Control	Section 8.2.182
3001h	MMD3_PCS_Status_1	PCS Status	Section 8.2.183

Complex bit access types are encoded to fit into small table cells. Table 8-4 shows the codes that are used for access types in this section.

Table 8-4 DP83TC815 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
R-0	R -0	Read Returns 0s
RC	R C	Read to Clear
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
W1S	W 1S	Write 1 to set
WSC	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.2.1 BMCR Register (Offset = 0h) [Reset = 2100h]

BMCR is shown in Table 8-5.

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Table 8-5 BMCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	MII Reset	R-0/W1S	0h	1b = Digital in reset and all MII regs (0x0 - 0xF) reset to default 0b = No reset This bit is auto-cleared
14	MII Loopback Enable	R/W	0h	1b = Enable MII loopback 0b = Disable MII loopback When xMII loopback mode is activated, the transmitted data presented on xMII TXD is looped back to xMII RXD internally. There is no LINK indication generated when xMII loopback is enabled.
13	Speed Select	R	1h	1b= 1000 Mb/s 0b = Reserved
12	Auto-Negotiation Enable	R	0h	Auto-Negotiation: Not supported on this device
11	IEEE Power Down Enable	R/W	0h	This bit can be programmed to enter and exit IEEE power down mode This bit provide status when using INT_N as power down pin 1b = Power down mode 0b = Normal mode
10	MAC Isolate Enable	R/W	0h	1b = Isolate mode (No output from PHY to MAC) 0b = Normal mode
9	RESERVED	R	0h	Reserved
8	Duplex Mode Select	R	1h	1b = Full duplex 0b = Half duplex
7	RESERVED	R	0h	Reserved
6-0	RESERVED	R	0h	Reserved

8.2.2 BMSR Register (Offset = 1h) [Reset = 0061h]

BMSR is shown in Table 8-6.

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Table 8-6 BMSR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	100Base-T4 Support	R	0h	0b = PHY does not support 100BASE-T4
14	100Base-X Full Duplex Support	R	0h	0b = PHY does not support full duplex 100BASE-X
13	100Base-X Half Duplex Support	R	0h	0b = PHY does not support half duplex 100BASE-X
12	10 Mbps Full Duplex Support	R	0h	0b = PHY does not support 10 Mb/s in full duplex mode
11	10 Mbps Half Duplex Support	R	0h	0b = PHY does not support 10 Mb/s in half duplex mode
10-7	RESERVED	R	0h	Reserved
6	SMI Preamble Suppression	R	1h	1b = PHY accepts management frames with preamble suppressed. 0b = PHY does not accept management frames with preamble suppressed
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	Auto-Negotiation Ability	R	0h	0b = PHY does not Auto-Negotiation
2	Link status (Latch Low)	RH	0h	1b = Link is up 0b = Link is down at least once
1	Jabber detect	RC	0h	1b = Jabber condition detected 0b = No Jabber condition detected
0	Extended register Capability	R	1h	1b = Extended register capabilities 0b = Basic register set capabilities only

8.2.3 PHYIDR1 Register (Offset = 2h) [Reset = 2000h]

PHYIDR1 is shown in Table 8-7.

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Table 8-7 PHYIDR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Organizationally Unique Identifier 1	R	2000h	Unique Identifier for the part

8.2.4 PHYIDR2 Register (Offset = 3h) [Reset = A2E0h]

PHYIDR2 is shown in Table 8-8.

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Table 8-8 PHYIDR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	Unique Identifier 2	R	28h	Unique Identifier for the part
9-4	Model Number	R	2Eh	Unique Identifier for the part
3-0	Revision Number	R	0h	Unique Identifier for the part

8.2.5 PHYSTS Register (Offset = 10h) [Reset = 0004h]

PHYSTS is shown in Table 8-9.

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Table 8-9 PHYSTS Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	Descrambler Lock Status (Latch Low)	RH	0h	1b = Descrambler is locked 0b = Descrmabler is unlocked at least once
8	RESERVED	R	0h	Reserved
7	Interrupt Pin Status	R	0h	Interrupts pin status, cleared on reading 0x12 1b = Interrupts pin not set 0b = Interrupt pin had been set
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	MII Loopback Status	R	0h	1b = MII loopback enabled 0b = MII loopback Disabled
2	Duplex Mode Status	R	1h	1b = Full duplex 0b = Half duplex
1	RESERVED	R	0h	Reserved
0	Link Status (Latch Low) Non-Clear on Read	R	0h	Non-Clear on Read Latch Low link status 1b = link is up 0b = link is down at least once Status is cleared on reading reg0x1

8.2.6 PHYSCR Register (Offset = 11h) [Reset = 010Bh]

PHYSCR is shown in Table 8-10.

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Table 8-10 PHYSCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13-12	RESERVED	R	0h	Reserved
11	SGMII Soft Reset	R/WSC	0h	SGMII Digital Reset This bit is auto-cleared
10	MAC Isolate for PHY_ADDR 0x00	R/W	0h	MAC Isolate is enabled only if PHY address is 0x00 Reg0x0[10] works for all PHY addresses including 0x00 1b = Isolate mode (No output from PHY to MAC) 0b = Normal mode
9-8	RMII TX FIFO Depth	R/W	1h	00b = 4 nibbles 01b = 5 nibbles 10b = 6 nibbles 11b = 8 nibbles
7	RESERVED	R	0h	Reserved
6-4	RESERVED	R	0h	Reserved
3	Interrupt Polarity	R/W	1h	1b = Active low 0b = Active high
2	Force Interrupt	R/W	0h	1b = Force interrupt pin
1	Interrupts Enable	R/W	1h	1b = Enable interrupts 0b = Disable interrupts
0	Interrupt Pin Configuration	R/W	1h	1b = Configure INT_N pin is as interrupt output pin 0b = Configure INT_N pin as power down input pin

8.2.7 MISR1 Register (Offset = 12h) [Reset = 0000h]

MISR1 is shown in Table 8-11.

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Table 8-11 MISR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	Energy Detect Change Status	RC	0h	Status is changed to 1 when there is a change of MDI Energy detection output Status is cleared on read of this register
13	Link Status Change Status	RC	0h	Status is changed to 1 when there is a change of link status Status is cleared on read of this register
12	Wake on LAN Status	RC	0h	Status is changed to 1 when WOL is received Status is cleared on read of this register
11	ESD Fault Detected Status	RC	0h	Status is changed to 1 when ESD fault is detected Status is cleared on read of this register
10	Training Done Status	RC	0h	Status is changed to 1 when training is done Status is cleared on read of this register
9	RESERVED	R	0h	Reserved
8	RX Error Counter Half Full Status	RC	0h	Status is changed to 1 when RX Error Counter in 0x15 is half full Status is cleared on read of this register
7	RESERVED	R	0h	Reserved
6	Energy Detect Change Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
5	Link Status Change Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
4	Wake on LAN Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
3	ESD Fault Detected Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
2	Training Done Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
1	RESERVED	R	0h	Reserved
0	RX Error Counter Half Full Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled

8.2.8 MISR2 Register (Offset = 13h) [Reset = 0000h]

MISR2 is shown in Table 8-12.

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Table 8-12 MISR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Under Voltage Status	RC	0h	Status is changed to 1 when Under Voltage is detected Status is cleared on read of this register
14	Over Voltage Status	RC	0h	Status is changed to 1 when Over Voltage is detected Status is cleared on read of this register
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	Over Temperature Status	RC	0h	Status is changed to 1 when Over Temperature is detected Status is cleared on read of this register
10	RESERVED	R	0h	Reserved
9	Data Polarity Change Status	RC	0h	Status is changed to 1 when MDI lines polarity change is detected Status is cleared on read of this register
8	Jabber Detect Status	RC	0h	Status is changed to 1 when jabber is detected Status is cleared on read of this register
7	Under Voltage Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
6	Over Voltage Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	Data Polarity Change Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
0	Jabber Detect Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled

8.2.9 RECR Register (Offset = 15h) [Reset = 0000h]

RECR is shown in Table 8-13.

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Table 8-13 RECR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RX Error Count	RC	0h	RX_ER Counter: When a valid carrier is presented (only while RX_DV is set), and there is at least one occurrence of an invalid data symbol, this 16-bit counter increments for each receive error detected. The RX_ER counter does not count in xMII loopback mode. The counter stops when it reaches its maximum count (0xFFFF). When the counter exceeds half-full (0x7FFF), an interrupt is generated. This register is cleared on read.

8.2.10 BISCR Register (Offset = 16h) [Reset = 0100h]

BISCR is shown in Table 8-14.

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Table 8-14 BISCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	Data Transmission to MDI in xMII Loopback	R/W	0h	0b = Suppress data to MDI during xMII loopback 1b = Transmit data to MDI during xMII loopback
5-2	Loopback Mode	R/W	0h	Enable Loopbacks other than PCS loopback. 0x16[1] must be 0 0001b = Digital Loopback 0010b = Analog Loopback 0100b = Reverse Loopback 1000b = External Loopback
1	PCS Loopback Enable	R/W	0h	0b = Disable PCS Loopback 1b = Enable PCS Loopback
0	RESERVED	R	0h	Reserved

8.2.11 MISR4 Register (Offset = 17h) [Reset = 0000h]

MISR4 is shown in Table 8-15.

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Table 8-15 MISR4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	PPM Monitor Unlock Status	R	0h	Status is changed to 1 when PPM Monitor unlocks Status is cleared on read of this register
10-7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	PPM Monitor Unlock Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
2-0	RESERVED	R	0h	Reserved

8.2.12 MISR3 Register (Offset = 18h) [Reset = 0035h]

MISR3 is shown in Table 8-16.

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Table 8-16 MISR3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	No Link Status	RC	0h	Status is changed to 1 when Link has not been observed within time programmed in 0x562 after training starts Status is cleared on read of this register
13	Sleep Fail Status	RC	0h	Status is changed to 1 when Sleep Negotiation Fails Status is cleared on read of this register
12	Power-On Reset Done Status	RC	0h	Status is changed to 1 Power-On Reset is done after the supplies are up Status is cleared on read of this register
11	No Frame Status	RC	0h	Status is changed to 1 when No frame is detected until Status is cleared on read of this register
10	WUR Received Status	RC	0h	Status is changed to 1 when WUR command is received from link partner Status is cleared on read of this register
9	Remote Wake-up Indication	RC	0h	Status is 1 after power-up if device is woken-up remotely Status is cleared on read of this register
8	LPS Received Status	RC	0h	Status is changed to 1 when LPS command is received from link partner Status is cleared on read of this register
7	RESERVED	R	0h	Reserved
6	No Link Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
5	Sleep Fail Indication	R/W	1h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
4	Power-On Reset Done Indication	R/W	1h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
3	No Frame Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
2	WUR Received Indication	R/W	1h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled
1	RESERVED	R	0h	Reserved
0	LPS Received Indication	R/W	1h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is Disabled

8.2.13 REG_19 Register (Offset = 19h) [Reset = 0800h]

REG_19 is shown in Table 8-17.

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Table 8-17 REG_19 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9-5	RESERVED	R	0h	Reserved
4-0	PHY Address	R	0h	PHY Address latched from straps

8.2.14 REG_1A Register (Offset = 1Ah) [Reset = 0000h]

REG_1A is shown in Table 8-18.

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Table 8-18 REG_1A Register Field Descriptions

Bit	Field	Type	Reset	Description
15-5	RESERVED	R	0h	Reserved
4	Data Polarity Status	R	0h	0b = Normal Polarity 1b = Reverse Polarity
3-1	RESERVED	R	0h	Reserved
0	Jabber Detect Disable	R/W	0h	0b = Jabber detection is enabled 1b =Jabber detection is Disabled

8.2.15 TC10_ABORT_REG Register (Offset = 1Bh) [Reset = 0000h]

TC10_ABORT_REG is shown in Table 8-19.

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Table 8-19 TC10_ABORT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	Sleep Abort through GPIO	R/W	0h	Sleep can be aborted by driving high on GPIO 1b = Use LED_1/CLKOUT for Sleep Abort (depending on which GPIO is configured as LED_1) 0b = GPIO is not used for Sleep Abort
0	Sleep Abort	R/W	0h	This bit to be set 1 to abort the sleep Cleared on transition to normal mode

8.2.16 CDCR Register (Offset = 1Eh) [Reset = 0000h]

CDCR is shown in Table 8-20.

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Table 8-20 CDCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	TDR Start	RH/W1S	0h	1b = Start TDR Bit is cleared after TDR run is complete
14	TDR Auto-Run Enable	R/W	0h	1b = Start TDR automatically on link down 0b = Start TDR manually using 0x1E[15]
13-2	RESERVED	R	0h	Reserved
1	TDR Done Status	R	0h	1b = TDR done 0b = TDR on-going or not initiated
0	TDR Fail status	R	0h	When TDR Done Status is 1, this bit indicates if TDR ran successfully 1b = TDR run failed 0b = TDR ran successfully

8.2.17 PHYRCR Register (Offset = 1Fh) [Reset = 0000h]

PHYRCR is shown in Table 8-21.

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Table 8-21 PHYRCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Hard Reset	R-0/W1S	0h	Resets Digital Core and register File This bet is self clearing
14	Soft Reset	R-0/W1S	0h	Resets Digital Core but register File is not reset This bit is self clearing
13	Soft Reset 2	R-0/W1S	0h	Resets register File This bit is self clearing
12	RESERVED	R	0h	Reserved
11-7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4-0	RESERVED	R	0h	Reserved

8.2.18 Register_3E (Offset = 3Eh) [Reset = 0000h]

Register_3E is shown in Table 8-22.

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Table 8-22 Register_3E Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5	cfg_leader_scr_rst_on_dsp_fail	R/W	0h	Enable Reset of scrambler on DSP fallback when phy is configured as Leader
4	cfg_follower_scr_rst_on_dsp_fail	R/W	0h	Enable Reset of scrambler on DSP fallback when phy is configured as Follower
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

8.2.19 Register_133 (Offset = 133h) [Reset = 0000h]

Register_133 is shown in Table 8-23.

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Table 8-23 Register_133 Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	Link Up Status	R	0h	Link Up status as defined by CnS
13	PHY Control In Send Data Mode	R	0h	PHY Control In Send Data Status
12	Link Status	R	0h	Link Status set by Link Monitor
11-8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	Descrambler Lock Status	R	0h	Descrambler lock status
1	Local Receiver Status	R	0h	Local receiver status
0	Remote Receiver Status	R	0h	Remote receiver status

8.2.20 Register_17F (Offset = 17Fh) [Reset = 4028h]

Register_17F is shown in Table 8-24.

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Table 8-24 Register_17F Field Descriptions

Bit	Field	Type	Reset	Description
15	WUR from WAKE pin	R/W	0h	Enable WUR transmission when a pulse is transmitted on WAKE pin 1b = Enable sending WUR Threshold of WAKE pulse width can be configured through 0x17F[7:0]
14	WUP Enable	R/W	1h	Enable WUP transmission after local wake 1b = WUP transmission is enabled 0b = WUP transmission is Disabled This option can be effectively used when PHY powers-up in Standby mode through strap
13-8	RESERVED	R	0h	Reserved
7-0	Wake Pulse Threshold	R/W	28h	Width of WAKE pulse in microseconds required to initiate WUR during an active link

8.2.21 Register_181 (Offset = 181h) [Reset = 0000h]

Register_181 is shown in Table 8-25.

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Table 8-25 Register_181 Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	RX LPS Count	R	0h	Indicates number of LPS codes received

8.2.22 Register_182 (Offset = 182h) [Reset = 0000h]

Register_182 is shown in Table 8-26.

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Table 8-26 Register_182 Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	RX WUR Count	R	0h	Indicates number of WUR codes received

8.2.23 LPS_CFG Register (Offset = 184h) [Reset = 0203h]

LPS_CFG is shown in Table 8-27.

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Table 8-27 LPS_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14-13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11-10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8-7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	Wake Forward Force	R/W	0h	1b = Force pulse on WAKE pin Pulse Width is configurable by bits [3:2] The bit is self-cleared
3-2	Wake Forward Pulse Width	R/W	0h	Configures the pulse width on WAKE pin for wake-forwarding 00b = 50us 01b = 500us 10b = 2ms 11b = 20ms
1	Wake Forward Enable	R/W	1h	Enable Wake Forwarding on WAKE pin on reception of WUR Command 0b = Enable Wake forwarding 1b = Disable Wake forwarding
0	RESERVED	R	0h	Reserved

8.2.24 LPS_CFG2 Register (Offset = 18Bh) [Reset = 1C4Bh]

LPS_CFG2 is shown in Table 8-28.

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Table 8-28 LPS_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	Stop Sleep Negotiation on Link Down	R/W	1h	1b = Stop Sleep Negotiation if link goes down during negotiation
11	Stop Sleep Negotiation on Activity	R/W	1h	1b = Stop Sleep Negotiation when activity from MAC is observed in SLEEP_ACK state
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	TC10 Disable	R/W	0h	0b = Enable TC10 1b = Disable TC10 Default value is decided by RX_CLK strap
7	RESERVED	R	0h	Reserved
6	Autonomous Mode	R/W	1h	1b = PHY entered normal mode on power up 0b = PHY entered standby mode on power up Default value is decided by LED_1 strap This bit is cleared post link up.
5	Transition To Standby	R/W	0h	1b = Enable normal to standby transition on over temperature/over voltage/under voltage 0b = Disable normal to standby transition on over temperature/over voltage/under voltage
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

8.2.25 LPS_CFG3 Register (Offset = 18Ch) [Reset = 0000h]

LPS_CFG3 is shown in Table 8-29.

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Table 8-29 LPS_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8-0	Power State Entry	RH/W1S	0h	00000001b = Normal command 00000010b = Sleep request 00010000b = Standby command 10000000b = WUR command

8.2.26 LINK_FAIL_CNT Register (Offset = 18Dh) [Reset = 0000h]

LINK_FAIL_CNT is shown in Table 8-30.

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Table 8-30 LINK_FAIL_CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	Link Losses Count	R	0h	TI Custom Link Loss Counter: Count incremented on fall edge of Link Status Count cleared on read of this register

8.2.27 LPS_STATUS Register (Offset = 18Eh) [Reset = 0000h]

LPS_STATUS is shown in Table 8-31.

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Table 8-31 LPS_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-7	RESERVED	R	0h	Reserved
6-0	Power State Status	R	0h	00000001b = Sleep Mode 00000010b = Standby Mode 00000100b = Normal Mode 00001000b = Sleep Ack 00010000b = Sleep Req 00100000b = Sleep Fail 01000000b = Sleep Silent

8.2.28 PCF Register (Offset = 1A0h) [Reset = 0000h]

PCF is shown in Table 8-32.

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Table 8-32 PCF Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	PHY Control Frames Error Status	R	0h	Indicates an error was detected in a PCF Frame since the last read of this register. This bit is cleared on read.
13	PHY Control Frames Ok Status	R	0h	Indicates a PCF Frame has completed without error since the last read of this register. This bit is cleared on read.
12-9	RESERVED	R	0h	Reserved
8	PHY Control Frames Destination Address	R/W	0h	Select MAC Destination Address for Phy Control Frames: 0: Use Mac Address [08 00 17 0B 6B 0F] 1: Use Mac Address [08 00 17 00 00 00] The device also recognizes packets with the above address with the Multicast bit set (that is 09 00 17)
7-6	PHY Control Frames Interrupt	R/W	0h	PCF Interrupt Control and Status: Bit 7 - Enable indication of PCF Frame Error Status on INT_N pin Bit 6 - Enable indication of PCF Frame OK Status on INT_N pin Status is available in 0x1A0[14:13]
5	PHY Control Frames Broadcast Disable	R/W	0h	By default, the device accepts broadcast Phy Control Frames which have a Phy address field of 0x1F. If this bit is set to a 1, the Phy Control Frame must have a Phy Address field that exactly matches the device Phy Address.
4-1	PHY Control Frames Buffer Size	R/W	0h	Determines the buffer size for transmit to allow Phy Control Frame detection. All packets are delayed as they pass through this buffer. If set to 0, packets are not be delayed and Phy Control frames are truncated after the Destination Address field
0	PHY Control Frames Enable	R/W	0h	Enables register writes using Phy Control Frames

8.2.29 MISC1 Register (Offset = 1A2h) [Reset = 0002h]

MISC1 is shown in Table 8-33.

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Table 8-33 MISC1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-7	RESERVED	R	0h	Reserved
6	Swap DA SA	R/W	0h	1b = Swap Destination Address and Source Address fields of the packet for debug
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3-0	RESERVED	R	0h	Reserved

8.2.30 PPM0 Register (Offset = 1A3h) [Reset = F423h]

PPM0 is shown in Table 8-34.

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Table 8-34 PPM0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Monitor Clock Count [15:0]	R/W	F423h	Lower 16 bits of Monitor clock counter in PPM Monitor Monitor Clock Count = Refresh period/monitor clock period Refresh period can be any common multiple of monitor and reference clock periods

8.2.31 PPM1 Register (Offset = 1A4h) [Reset = 0000h]

PPM1 is shown in Table 8-35.

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Table 8-35 PPM1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Monitor Clock Count [31:16]	R/W	0h	Higher 16 bits of Monitor clock counter in PPM Monitor Monitor Clock Count = Refresh period/monitor clock period Refresh period can be any common multiple of monitor and reference clock periods

8.2.32 PPM2 Register (Offset = 1A5h) [Reset = 30D3h]

PPM2 is shown in Table 8-36.

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Table 8-36 PPM2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Reference Clock Count [15:0]	R/W	30D3h	Lower 16 bits of Reference clock counter in PPM Monitor Reference Clock Count = Refresh period/reference clock period Refresh period can be any common multiple of monitor and reference clock periods

8.2.33 PPM3 Register (Offset = 1A6h) [Reset = 0000h]

PPM3 is shown in Table 8-37.

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Table 8-37 PPM3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Reference Clock Count [31:16]	R/W	0h	Higher 16 bits of Reference clock counter in PPM Monitor Reference Clock Count = Refresh period/reference clock period Refresh period can be any common multiple of monitor and reference clock periods

8.2.34 PPM4 Register (Offset = 1A7h) [Reset = 0000h]

PPM4 is shown in Table 8-38.

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Table 8-38 PPM4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PPM Monitor Interrupt Threshold Count - 1 [15:0]	R/W	0h	Lower 16 bits of PPM Monitor Interrupt Threshold Count - 1: PPM Monitor Interrupt Threshold Count 1 = Monitor Clock Count PPM beyond which interrupt must be flagged

8.2.35 PPM5 Register (Offset = 1A8h) [Reset = 0000h]

PPM5 is shown in Table 8-39.

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Table 8-39 PPM5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PPM Monitor Interrupt Threshold Count - 1 [31:16]	R/W	0h	Higher 16 bits of PPM Monitor Interrupt Threshold Count -1: PPM Monitor Interrupt Threshold Count 1 = Monitor Clock Count PPM beyond which interrupt must be flagged

8.2.36 PPM6 Register (Offset = 1A9h) [Reset = 0000h]

PPM6 is shown in Table 8-40.

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Table 8-40 PPM6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PPM Monitor Interrupt Threshold Count - 2 [15:0]	R/W	0h	Lower 16 bits of PPM Monitor Interrupt Threshold Count - 2: PPM Monitor Interrupt Threshold Count 2 = Monitor clock count - (Monitor Clock Count negative PPM beyond which interrupt must be flagged)

8.2.37 PPM7 Register (Offset = 1AAh) [Reset = 0000h]

PPM7 is shown in Table 8-41.

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Table 8-41 PPM7 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PPM Monitor Interrupt Threshold Count - 2 [31:16]	R/W	0h	Higher 16 bits of PPM Monitor Interrupt Threshold Count -2: PPM Monitor Interrupt Threshold Count 2 = Monitor clock count - (Monitor Clock Count negative PPM beyond which interrupt must be flagged)

8.2.38 PPM10 Register (Offset = 1ADh) [Reset = 0000h]

PPM10 is shown in Table 8-42.

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Table 8-42 PPM10 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PPM Monitor Output [15:0]	R/W	0h	PPM Monitor output If 0x01AE[15] = 0, ppm offset is negative, if 0x01AE[15] = 1, ppm offset is positive PPM offset of monitor clock = {0x01AE[14:0],0x01AD[15:0]}/ {0x01A4, 0x01A3}

8.2.39 PPM11 Register (Offset = 1AEh) [Reset = 0000h]

PPM11 is shown in Table 8-43.

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Table 8-43 PPM11 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PPM Monitor Output [31:16]	R/W	0h	PPM Monitor output If 0x01AE[15] = 0, ppm offset is negative, if 0x01AE[15] = 1, ppm offset is positive PPM offset of monitor clock = {0x01AE[14:0],0x01AD[15:0]}/ {0x01A4, 0x01A3}

8.2.40 PPM12 Register (Offset = 1AFh) [Reset = 0000h]

PPM12 is shown in Table 8-44.

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Table 8-44 PPM12 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	PPM Monitor External Clock Select	R/W	0h	Selects GPIO pin for External Clock Input of PPM Monitor: 2h = LED_0 3h = GPIO5
13	PPM Monitor Enable	R/W	0h	Enable for PPM monitor: 0h = Disable PPM Monitor 1h = Enable PPM Monitor
12-9	Reference Clock Select for PPM Monitor	R/W	0h	Selects the reference clock for the PPM monitor 0h = XI Input 1h = 200MHz Recovered Clock 2h = PLL CLK of 250MHz 3h = PTP PLL 4h = External Clock Input 5h = 200MHz Leader Transmit Clock 6h = SGMII Recovered Clock 7h = PTP Trigger 0
8-5	Monitor Clock Select for PPM Monitor	R/W	0h	Selects the monitor clock for the PPM monitor 0h = XI Input 1h = 200MHz Recovered Clock 2h = PLL CLK of 250Mhz 3h = PTP PLL 4h = External Clock Input 5h = 200MHz Leader Transmit Clock 6h = SGMII Recovered Clock 7h = PTP Trigger 0
4	Latch PPM Monitor Value	R/W	0h	Latches the ppm monitor value to a shadow register 0h = Disable PPM Status Read 1h = Enable PPM Status Read
3-2	RESERVED	R	0h	Reserved
1-0	RESERVED	R	0h	Reserved

8.2.41 fwu_reg_3 Register (Offset = 1BEh) [Reset = 0158h]

fwu_reg_3 is shown in Table 8-45.

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Table 8-45 fwu_reg_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	Fast Wake-Up Memory Load Enable	R/W	0h	Program this bit to 1 to enable loading register address and data into the memory
9	Fast Wake-Up Load Trigger	R/W	0h	Program this bit to 1 after programming register Address and Data in 0x1BC and 0x1BD This bit is auto-clearing
8	Fast Wake-Up Memory Reset	R/W	1h	0h = Reset Memory
7-2	RESERVED	R	0h	Reserved
1-0	RESERVED	R	0h	Reserved

8.2.42 spare_reg_tc10 Register (Offset = 1D2h) [Reset = 0000h]

spare_reg_tc10 is shown in Table 8-46.

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Table 8-46 spare_reg_tc10 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Configure Fast Wake-Up	R/W	0h	To enable fast wake-up Memory program 0x01D2 = 0x0004 0x01D2 = 0x0014 0x01D2 = 0x0004

8.2.43 TDR_TC1 Register (Offset = 310h) [Reset = 0000h]

TDR_TC1 is shown in Table 8-47.

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Table 8-47 TDR_TC1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	Fault Detect Status	R	0h	1b = Fault detected in cable 0b = No Fault detected in cable
6	Fault Type	R	0h	0b = Short to GND, supply, or between MDI pins 1b = Open. Applicable to both 1-wire and 2-wire open faults
5-0	TDR Fault Location	R	0h	Fault location in meters (Valid only if Fault Detect Status = 1)

8.2.44 ANA_LD_CTRL_3 Register (Offset = 402h) [Reset = 0000h]

ANA_LD_CTRL_3 is shown in Table 8-48.

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Table 8-48 ANA_LD_CTRL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	VDDIO Supply Level	R	0h	VDDIO Level Detected by the PHY: 00b = 1.8V VDDIO 01b = 2.5V VDDIO 11b = 3.3V VDDIO
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11-10	VDDMAC Supply Level	R	0h	VDDIO Level Detected by the PHY: 00b = 1.8V VDDMAC 01b = 2.5V VDDMAC 11b = 3.3V VDDMAC
9-8	RESERVED	R	0h	Reserved
7-4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2-0	RESERVED	R	0h	Reserved

8.2.45 A2D_REG_48 Register (Offset = 430h) [Reset = 0AA0h]

A2D_REG_48 is shown in Table 8-49.

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Table 8-49 A2D_REG_48 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11-8	RGMII TX Shift Delay	R/W	Ah	Controls Internal Delay in RGMII mode in Steps of 312.5ps Delay = ((Bit[7:4] in decimal) + 1) x 312.5 ps
7-4	RGMII RX Shift Delay	R/W	Ah	Controls Internal Delay in RGMII mode in Steps of 312.5ps Delay = ((Bit[7:4] in decimal) + 1) x 312.5 ps
3-0	RESERVED	R	0h	Reserved

8.2.46 A2D_REG_64 Register (Offset = 440h) [Reset = 0001h]

A2D_REG_64 is shown in Table 8-50.

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Table 8-50 A2D_REG_64 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14-5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	ESD Event Counter Disable	R/W	1h	1b = Disable ESD Counter 0b = Enable ESD Counter Toggle this bit to clear the ESD counter

8.2.47 A2D_REG_66 Register (Offset = 442h) [Reset = 0000h]

A2D_REG_66 is shown in Table 8-51.

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Table 8-51 A2D_REG_66 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14-9	ESD Event Count	R	0h	Field gives the number of ESD events on the copper channel
8	RESERVED	R	0h	Reserved
7-5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3-0	RESERVED	R	0h	Reserved

8.2.48 A2D_REG_68 Register (Offset = 444h) [Reset = 0000h]

A2D_REG_68 is shown in Table 8-52.

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Table 8-52 A2D_REG_68 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3	Sleep Force Value	R/W	0h	1b = Force Sleep when Sleep Force Enable is set to 1
2	Sleep Force Enable	R/W	0h	1b = Sleep Force Enable (Sleep Force Value has to be set)
1	WAKE pin Force Value	R/W	0h	Force value on WAKE pin when WAKE pin Force Enable is set 1b = High 0b = Low
0	WAKE pin Force Enable	R/W	0h	1b = Enable Force control of WAKE pin

8.2.49 LEDS_CFG_1 Register (Offset = 450h) [Reset = 2610h]

LEDS_CFG_1 is shown in Table 8-53.

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Table 8-53 LEDS_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	Disable LED Stretching	R/W	0h	0b = LED pulses are stretched according to the blink rate in 'LED Blink Rate' field 1b = LED pulses are directly connected to RX_DV(for RX activity) and TX_CTRL(for TX Activity)
13-12	LED Blink Rate	R/W	2h	Blink Rate of the LED when configured for activity 00b = 20Hz (50 ms) 01b = 10Hz (100 ms) 10b = 5Hz (200 ms) 11b = 2Hz (500 ms)
11-8	LED_2 Options	R/W	6h	0x0 : link OK 0x1 : link OK + blink on TX/RX activity 0x2 : link OK + blink on TX activity 0x3 : link OK + blink on RX activity 0x4 : link OK + 100Base-T1 Leader 0x5 : link OK + 100Base-T1 Follower 0x6 : TX/RX activity with stretch option 0x7 : Reserved 0x8 : Reserved 0x9 : Link lost (remains on until register 0x1 is read) 0xB : xMII TX/RX Error with stretch option
7-4	LED_1 Options	R/W	1h	0x0 : link OK 0x1 : link OK + blink on TX/RX activity 0x2 : link OK + blink on TX activity 0x3 : link OK + blink on RX activity 0x4 : link OK + 100Base-T1 Leader 0x5 : link OK + 100Base-T1 Follower 0x6 : TX/RX activity with stretch option 0x7 : Reserved 0x8 : Reserved 0x9 : Link lost (remains on until register 0x1 is read) 0xB : xMII TX/RX Error with stretch option
3-0	LED_0 Options	R/W	0h	0x0 : link OK 0x1 : link OK + blink on TX/RX activity 0x2 : link OK + blink on TX activity 0x3 : link OK + blink on RX activity 0x4 : link OK + 100Base-T1 Leader 0x5 : link OK + 100Base-T1 Follower 0x6 : TX/RX activity with stretch option 0x7 : Reserved 0x8 : Reserved 0x9 : Link lost (remains on until register 0x1 is read) 0xB : xMII TX/RX Error with stretch option

8.2.50 LEDS_CFG_2 Register (Offset = 451h) [Reset = 0009h]

LEDS_CFG_2 is shown in Table 8-54.

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Table 8-54 LEDS_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12-9	RESERVED	R	0h	Reserved
8	LED_2 Force Enable	R/W	0h	1b = Force 'LED_2 Force Value' on CLKOUT pin (when CLKOUT is configured as LED_2)
7	LED_2 Force Value	R/W	0h	When LED_2 Force Enable is set, this bit decides the output of LED_2 0b = Low 1b = High
6	LED_2 Polarity	R/W	0h	Polarity of LED_2: (When CLKOUT is used as LED_2) 0b = Active Low polarity 1b = Active High polarity
5	LED_1 Force Enable	R/W	0h	1b = Force 'LED_1 Force Value' on LED_1 pin
4	LED_1 Force Value	R/W	0h	When LED_1 Force Enable is set, this bit decides the output of LED_1 0b = Low 1b = High
3	LED_1 Polarity	R/W	1h	Polarity of LED_1: 0b = Active Low polarity 1b = Active High polarity Default value is decided by the strap on LED_1. If the strap is placed to supply, LED_1 polarity is 0, else LED_1 polarity is 1.
2	LED_0 Force Enable	R/W	0h	1b = Force 'LED_0 Force Value' on LED_0 pin
1	LED_0 Force Value	R/W	0h	When LED_0 Force Enable is set, this bit decides the output of LED_0 0b = Low 1b = High
0	LED_0 Polarity	R/W	1h	Polarity of LED_0: 0b = Active Low polarity 1b = Active High polarity Default value is decided by the strap on LED_0. If the strap is placed to supply, LED_0 polarity is 0, else LED_0 polarity is 1

8.2.51 IO_MUX_CFG_1 Register (Offset = 452h) [Reset = 0000h]

IO_MUX_CFG_1 is shown in Table 8-55.

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Table 8-55 IO_MUX_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10-8	LED_1 Configuration	R/W	0h	000b = (default: LINK) 010b = WoL 011b = Under-Voltage indication 110b = ESD 111b = interrupt
7	RESERVED	R	0h	Reserved
6-4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2-0	LED_0 Configuration	R/W	0h	000b = (default: LINK) 010b = WoL 011b = Under-Voltage indication 110b = ESD 111b = interrupt

8.2.52 IO_MUX_CFG_2 Register (Offset = 453h) [Reset = 0001h]

IO_MUX_CFG_2 is shown in Table 8-56.

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Table 8-56 IO_MUX_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Enable TX_ER on LED_1	R/W	0h	Configures LED_1 pin to TX_ER
14-9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7-4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2-0	CLKOUT Configuration	R/W	1h	000b = (default: LINK) 010b = WoL 011b = Under-Voltage indication 110b = ESD 111b = interrupt

8.2.53 IO_CONTROL_2 Register (Offset = 455h) [Reset = 0000h]

IO_CONTROL_2 is shown in Table 8-57.

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Table 8-57 IO_CONTROL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13-9	Impedance Control - LED_0, GPIO_5	R/W	0h	00000b - Fast Mode (Default) 00001b - Slow Mode
8-7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4-2	RESERVED	R	0h	Reserved
1-0	RESERVED	R	0h	Reserved

8.2.54 IO_MUX_CFG Register (Offset = 456h) [Reset = 0021h]

IO_MUX_CFG is shown in Table 8-58.

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Table 8-58 IO_MUX_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12-11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9-5	Impedance Control - RX pins	R/W	1h	Impedance control for RX_CLK, RX_D[3:0], RX_CTRL, RX_ER 1h = Slew Mode -1 2h = Slew Mode -2 3h = Slew Mode -3 4h = Slew Mode -4 5h = Slew Mode -5 6h = Slew Mode -6 7h = Slew Mode -7
4-0	Impedance Control - TX_CLK	R/W	1h	1h = Slew Mode -1 2h = Slew Mode -2 3h = Slew Mode -3 4h = Slew Mode -4 5h = Slew Mode -5 6h = Slew Mode -6 7h = Slew Mode -7

8.2.55 CHIP_SOR_1 Register (Offset = 45Dh) [Reset = 0000h]

CHIP_SOR_1 is shown in Table 8-59.

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Table 8-59 CHIP_SOR_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	GPIO_4 Strap	R	0h	GPIO_4 strap sampled at power up or reset
14	RESERVED	R	0h	Reserved
13	LED_1 Strap	R	0h	LED_1 strap sampled at power up
12	RX_D3 Strap	R	0h	RX_D3 strap sampled at power up
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	LED0 Strap	R	0h	LED_0 strap sampled at power up or reset
8	RXD3 Strap	R	0h	RX_D3 strap sampled at reset
7	RXD2 Strap	R	0h	RX_D2 strap sampled at power up or reset
6	RXD1 Strap	R	0h	RX_D1 strap sampled at power up or reset
5	RXD0 Strap	R	0h	RX_D0 strap sampled at power up or reset
4	RXCLK Strap	R	0h	RX_CLK strap sampled at power up or reset
3-2	RXER Strap	R	0h	RX_ER strap sampled at power up or reset
1-0	RXDV Strap	R	0h	RX_DV strap sampled at power up or reset

8.2.56 LED1_CLKOUT_ANA_CTRL Register (Offset = 45Fh) [Reset = 000Ch]

LED1_CLKOUT_ANA_CTRL is shown in Table 8-60.

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Table 8-60 LED1_CLKOUT_ANA_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13-5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3-2	LED_1 Mux Control	R/W	3h	00b = 25MHz XI Clock for daisy chaining 01b = TX_TCLK for test modes 11b = Signal Selected by CLKOUT Configuration
1-0	CLKOUT Mux Control	R/W	0h	00b = 25MHz XI Clock for daisy chaining 01b = TX_TCLK for test modes 11b = Signal Selected by CLKOUT Configuration

8.2.57 IMPEDANCE_CTRL_0 Register (Offset = 460h) [Reset = 0101h]

IMPEDANCE_CTRL_0 is shown in Table 8-61.

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Table 8-61 IMPEDANCE_CTRL_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12-8	Impedance Control - CLK_OUT	R/W	1h	1h = Slew Mode -1 2h = Slew Mode -2 3h = Slew Mode -3 4h = Slew Mode -4 5h = Slew Mode -5 6h = Slew Mode -6 7h = Slew Mode -7
7-5	RESERVED	R	0h	Reserved
4-0	Impedance Control - LED_1	R/W	1h	1h = Slew Mode -1 2h = Slew Mode -2 3h = Slew Mode -3 4h = Slew Mode -4 5h = Slew Mode -5 6h = Slew Mode -6 7h = Slew Mode -7

8.2.58 IMPEDANCE_CTRL_1 Register (Offset = 461h) [Reset = 0101h]

IMPEDANCE_CTRL_1 is shown in Table 8-62.

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Table 8-62 IMPEDANCE_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12-8	Impedance Control - GPIO_4	R/W	1h	1h = Slew Mode -1 2h = Slew Mode -2 3h = Slew Mode -3 4h = Slew Mode -4 5h = Slew Mode -5 6h = Slew Mode -6 7h = Slew Mode -7
7-5	RESERVED	R	0h	Reserved
4-0	Impedance Control - GPIO_3	R/W	1h	1h = Slew Mode -1 2h = Slew Mode -2 3h = Slew Mode -3 4h = Slew Mode -4 5h = Slew Mode -5 6h = Slew Mode -6 7h = Slew Mode -7

8.2.59 RX_FIFO_CONFIG Register (Offset = 4DFh) [Reset = 0003h]

RX_FIFO_CONFIG is shown in Table 8-63.

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Table 8-63 RX_FIFO_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3-0	cfg_sync_fifo_wr_cnt_rst_val	R/W	3h

8.2.60 LINKUP_TIMER_1 Register (Offset = 4EEh) [Reset = 0000h]

LINKUP_TIMER_1 is shown in Table 8-64.

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Table 8-64 LINKUP_TIMER_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Link Up Timer [15:0]	R	0h	Link Up timer calculated from Power-up or Soft Reset or Link Down whichever comes later Link Up time (in ns) = Link Up Timer [31:0]*40

8.2.61 LINKUP_TIMER_2 Register (Offset = 4EFh) [Reset = 0000h]

LINKUP_TIMER_2 is shown in Table 8-65.

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Table 8-65 LINKUP_TIMER_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Link Up Timer [31:16]	R	0h	Link Up timer calculated from Power-up or Soft Reset or Link Down whichever comes later Link Up time (in ns) = Link Up Timer [31:0]*40

8.2.62 TX_PR_FILT_CTRL Register (Offset = 523h) [Reset = 0000h]

TX_PR_FILT_CTRL is shown in Table 8-66.

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Table 8-66 TX_PR_FILT_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	MDI Polarity Invert	R/W	0h	1b = Invert polarity on MDI transmit side
0	MDI Transmit Disable	R/W	0h	1b = Disable Transmit on MDI 0b = Enable Transmit on MDI

8.2.63 PG_REG_1 Register (Offset = 551h) [Reset = 0010h]

PG_REG_1 is shown in Table 8-67.

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Table 8-67 PG_REG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-5	RESERVED	R	0h	Reserved
4	RMII CRS_DV Config	R/W	1h	Configure Pin 15 as RX_DV or CRS_DV: 1b = Pin15 is CRS_DV 0b = Pin 15 is RX_DV
3-0	RESERVED	R	0h	Reserved

8.2.64 PG_REG_3 Register (Offset = 552h) [Reset = 0008h]

PG_REG_3 is shown in Table 8-68.

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Table 8-68 PG_REG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R	0h	Reserved

8.2.65 PG_REG_4 Register (Offset = 553h) [Reset = 0000h]

PG_REG_4 is shown in Table 8-69.

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Table 8-69 PG_REG_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	Force Receive Polarity Force Enable	R/W	0h	0x0553[13:12] = 2'b10 : Disable Auto-Polarity Correction and force no polarity inversion 0x0553[13:12] = 2'b11 : Disable Auto-Polarity Correction and force polarity inversion
12	Receive polarity Force Value	R/W	0h	0x0553[13:12] = 2'b10 : Disable Auto-Polarity Correction and force no polarity inversion 0x0553[13:12] = 2'b11 : Disable Auto-Polarity Correction and force polarity inversion
11-0	RESERVED	R	0h	Reserved

8.2.66 TC1_LINK_FAIL_LOSS Register (Offset = 561h) [Reset = 0000h]

TC1_LINK_FAIL_LOSS is shown in Table 8-70.

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Table 8-70 TC1_LINK_FAIL_LOSS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	Link Losses	R	0h	Number of Link Losses as defined in TC1 since last power cycle
9-0	Link Failures	R	0h	Link Failures as defined in TC1 Number of Link Failures (including RX errors, Bad SSD, Bad ESD, Bad SQI) not causing a link down

8.2.67 TC1_LINK_TRAINING_TIME Register (Offset = 562h) [Reset = 0000h]

TC1_LINK_TRAINING_TIME is shown in Table 8-71.

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Table 8-71 TC1_LINK_TRAINING_TIME Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Communication Ready	R	0h	Communication ready as defined in TC1 1b = PHY is ready for communication
14-8	RESERVED	R	0h	Reserved
7-0	Link Training Time	R	0h	Link Training Time measured in milliseconds measured from soft reset

8.2.68 NO_LINK_TH Register (Offset = 563h) [Reset = 0096h]

NO_LINK_TH is shown in Table 8-72.

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Table 8-72 NO_LINK_TH Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	No Link Timer Threshold	R/W	96h	Time Threshold in milliseconds for No Link Interrupt

8.2.69 DITH_CTRL_0 Register (Offset = 5A0h) [Reset = 3042h]

DITH_CTRL_0 is shown in Table 8-73.

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Table 8-73 DITH_CTRL_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	Dithering Direction	R/W	0h	Selects type of Sawtooth profile 0h = Reverse Sawtooth profile 1h = Increasing Sawtooth profile
7-4	RESERVED	R	0h	Reserved
3-0	RESERVED	R	0h	Reserved

8.2.70 DITH_CTRL_1 Register (Offset = 5A1h) [Reset = 640Dh]

DITH_CTRL_1 is shown in Table 8-74.

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Table 8-74 DITH_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	Dithering Frequency Step	R/W	64h	Configure the maximum frequency offset for dithering 0x05A1[15:8] = (Required (delta(f)/f) *2¹⁷)/(0x5A1[7:0]) Default delta(f)/f = 1% Keep delta(f)/f limited to ≤ 2%
7-0	Dithering Modulation Period	R/W	Dh	Configures the modulation period for dithering 0x5A1[7:0] = Dithering Modulation Period / 640 ns) Default Modulation Period = 13*640ns = 8.34 us

8.2.71 DITH_RFI_EN_CTRL Register (Offset = 5A8h) [Reset = 0D07h]

DITH_RFI_EN_CTRL is shown in Table 8-75.

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Table 8-75 DITH_RFI_EN_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	Dithering Profile	R/W	0h	Select Dithering Frequency Profile 0h = Sawtooth 1h = Triangular
13	RESERVED	R	0h	Reserved
12	Dithering Enable	R/W	0h	1b = Enable Clock Dithering Engine
11	MAC Interface Dithering Enable	R/W	1h	1b = Enable dithering of RMII, RGMII, MII MAC Interface Outputs
10	Core Clocks Dithering Enable	R/W	1h	1b = Enable dithering for Internal Digital clocks
9-0	RESERVED	R	0h	Reserved

8.2.72 CFG_PCF_DMAC_ADDR Register (Offset = 5B2h) [Reset = 0F6Bh]

CFG_PCF_DMAC_ADDR is shown in Table 8-76.

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Table 8-76 CFG_PCF_DMAC_ADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	cfg_pcf_dmac_addr	R/W	F6Bh	Configurable last two bytes of PCF DMAC

8.2.73 SPARE_IN_FROM_DIG_SL_1 Register (Offset = 5B7h) [Reset = 0043h]

SPARE_IN_FROM_DIG_SL_1 is shown in Table 8-77.

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Table 8-77 SPARE_IN_FROM_DIG_SL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reads zero
11-0	spare_in_fromdig_sl_1	R/W	43h	register with configurable bits for analog

8.2.74 CONTROL_REG_1 Register (Offset = 5B8h) [Reset = 0001h]

CONTROL_REG_1 is shown in Table 8-78.

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Table 8-78 CONTROL_REG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5	cfg_dith_dis_till_linkup	R/W	0h	1b = Dithering is Disabled till linkup 0b = Dithering enabled before linkup
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

8.2.75 RGMII_CTRL Register (Offset = 600h) [Reset = 002Xh]

RGMII_CTRL is shown in Table 8-79.

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Table 8-79 RGMII_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-7	RESERVED	R	0h	Reserved
6-4	RGMII TX FIFO Half Full Threshold	R/W	2h	RGMII TX sync FIFO half full threshold
3	RGMII Enable	R/W	0h	1b = RGMII enable 0b = RGMII Disable Default value is latched from straps
2	Invert RGMII TX Data Lines	R/W	0h	1b = Invert RGMII TXD[3:0] TX_D3 to TX_D0 TX_D2 to TX_D1 TX_D1 to TX_D2 TX_D0 to TX_D3
1	Invert RGMII RX Data Lines	R/W	0h	1b = Invert RGMII RXD[3:0] RX_D3 to RX_D0 RX_D2 to RX_D1 RX_D1 to RX_D2 RX_D0 to RX_D3
0	RESERVED	R	0h	Reserved

8.2.76 RGMII_FIFO_STATUS Register (Offset = 601h) [Reset = 0000h]

RGMII_FIFO_STATUS is shown in Table 8-80.

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Table 8-80 RGMII_FIFO_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	RGMII TX FIFO Full Error	R	0h	1b = RGMII TX full error has been indicated 0b = No empty fifo error This bit is only cleared on device reset
0	RGMII TX FIFO Empty Error	R	0h	1b = RGMII TX empty error has been indicated 0b = No empty fifo error This bit is only cleared on device reset

8.2.77 RGMII_CLK_SHIFT_CTRL Register (Offset = 602h) [Reset = 000Xh]

RGMII_CLK_SHIFT_CTRL is shown in Table 8-81.

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Table 8-81 RGMII_CLK_SHIFT_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	RGMII RX Shift	R/W	0h	0b = clock and data are aligned 1b = clock is internally delayed by value programmed in DLL RX Shift Delay
0	RGMII TX Shift	R/W	0h	0b = clock and data are aligned 1b = clock is internally delayed by value programmed in DLL TX Shift Delay

8.2.78 SGMII_CTRL_1 Register (Offset = 608h) [Reset = 0X7Bh]

SGMII_CTRL_1 is shown in Table 8-82.

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Table 8-82 SGMII_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	SGMII TX Error Disable	R/W	0h	1b = Disable SGMII TX Error indication 0b = Enable SGMII TX Error indication
14	RESERVED	R	0h	Reserved
13-10	RESERVED	R	0h	Reserved
9	SGMII Enable	R/W	0h	1b = SGMII enable 0b = SGMII Disable Default value is latched from straps If both SGMII and RGMII are enabled, SGMII take precedence
8	SGMII TX polarity Invert	R/W	0h	1b = Invert SGMII RX_D[3:2] polarity
7	SGMII TX polarity Invert	R/W	0h	1b = Invert SGMII TX_D[1:0] polarity
6-5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2-1	RESERVED	R	0h	Reserved
0	SGMII Auto Negotiation Enable	R/W	1h	1b = Enable SGMII Auto-Negotaition 0b = Disable SGMII Auto-Negotiation

8.2.79 SGMII_STATUS Register (Offset = 60Ah) [Reset = 0000h]

SGMII_STATUS is shown in Table 8-83.

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Table 8-83 SGMII_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	SGMII Page Received	R	0h	1b = A new auto neg page received 0b = No new auto neg page received
11	SGMII Link Status	R	0h	1b = SGMII link up 0b = SGMII link down
10	SGMII Auto Negotiation Status	R	0h	1b = SGMII autoneg completed
9	Word Boundary Align Indication	R	0h	1b = Aligned
8	Word Boundary Sync Status	R	0h	1b = sync achieved 0b = sync not achieved
7-4	RESERVED	R	0h	Reserved
3-0	RESERVED	R	0h	Reserved

8.2.80 SGMII_CTRL_2 Register (Offset = 60Ch) [Reset = 0044h]

SGMII_CTRL_2 is shown in Table 8-84.

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Table 8-84 SGMII_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7-4	SGMII TX FIFO Half Full Threshold	R/W	4h	SGMII TX sync FIFO half full threshold
3-0	SGMII RX FIFO Half Full Threshold	R/W	4h	SGMII RX sync FIFO half full threshold

8.2.81 SGMII_FIFO_STATUS Register (Offset = 60Dh) [Reset = 0000h]

SGMII_FIFO_STATUS is shown in Table 8-85.

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Table 8-85 SGMII_FIFO_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3	SGMII RX FIFO Full Error	RC	0h	1b = SGMII RX fifo full error has been indicated 0b = No error indication
2	SGMII RX FIFO Empty Error	RC	0h	1b = SGMII RX fifo empty error has been indicated 0b = No error indication
1	SGMII TX FIFO Full Error	RC	0h	1b = SGMII TX fifo full error has been indicated 0b = No error indication
0	SGMII TX FIFO Empty Error	RC	0h	1b = SGMII TX fifo empty error has been indicated 0b = No error indication

8.2.82 PRBS_STATUS_1 Register (Offset = 618h) [Reset = 0000h]

PRBS_STATUS_1 is shown in Table 8-86.

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Table 8-86 PRBS_STATUS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	PRBS Error Overflow Counter	R	0h	Holds number of error counter overflow that received by the PRBS checker. Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. Counter stops on 0xFF. Note: when PRBS counters work in single mode, overflow counter is not active

8.2.83 PRBS_CTRL_1 Register (Offset = 619h) [Reset = 0574h]

PRBS_CTRL_1 is shown in Table 8-87.

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Table 8-87 PRBS_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	Send Packet	R-0/W1S	0h	Enables generating MAC packet with fix/incremental data with CRC (0x619[0] has to be set and 0x619[1] has to be clear) Cleared automatically when pkt_done is set 1b = Transmit MAC packet with CRC 0b = Stop MAC packet
11	RESERVED	R	0h	Reserved
10-8	PRBS Check Select	R/W	5h	Selects the direction of PRBS checker reception 000b = Checker receives from RGMII TX 001b = Checker receives SGMII TX 101b = Checker receives from MDI RX
7	RESERVED	R	0h	Reserved
6-4	PRBS Transmit Select	R/W	7h	Selects the direction of PRBS transmission 000b = PRBS transmits to RGMII RX 001b = PRBS transmits to SGMII RX 101b = PRBS transmits to MDI TX
3	PRBS Count Mode	R/W	0h	1b = Continuous mode, when one of the PRBS counters reaches max value, pulse is generated and counter starts counting from zero again 0b = Single mode, When one of the PRBS counters reaches max value, PRBS checker stops counting.
2	PRBS Checker Enable	R/W	1h	Enable PRBS checker (to receive data) To be enabled for counters in 0x63C, 0x63D, 0x63E to work 1b = Enable PRBS checker
1	PRBS Generation Enable	R/W	0h	If 0x619[0] is set, 1b = Transmits PRBS packet 0b = Transmits non-PRBS packet (PRBS checker is also Disabled in this case)
0	PRBS or Packet Generation Enable	R/W	0h	1b = Enable packet/PRBS generator 0b = Disable packet/PRBS generator

8.2.84 PRBS_CTRL_2 Register (Offset = 61Ah) [Reset = 05DCh]

PRBS_CTRL_2 is shown in Table 8-88.

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Table 8-88 PRBS_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Packet Length	R/W	5DCh	Sets packet length (in bytes) between the PRBS packets or non-PRBS packets generated

8.2.85 PRBS_CTRL_3 Register (Offset = 61Bh) [Reset = 007Dh]

PRBS_CTRL_3 is shown in Table 8-89.

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Table 8-89 PRBS_CTRL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	PRBS IPG	R/W	7Dh	Sets IPG (in bytes) between the PRBS packets or non-PRBS packets generated

8.2.86 PRBS_STATUS_2 Register (Offset = 61Ch) [Reset = 0000h]

PRBS_STATUS_2 is shown in Table 8-90.

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Table 8-90 PRBS_STATUS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS Checker Byte Count	R	0h	Holds number of total bytes that received by the PRBS checker Value in register is locked when 0x620[0] or 0x620[1] are written When PRBS Count Mode set to zero, count stops on 0xFFFF This counter is cleared if this counter is read after programming 0x620[1]=1

8.2.87 PRBS_STATUS_3 Register (Offset = 61Dh) [Reset = 0000h]

PRBS_STATUS_3 is shown in Table 8-91.

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Table 8-91 PRBS_STATUS_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS Checker Packet Count-1	R	0h	Holds Bits [15:0] of number of total packets received by the PRBS checker Value in register is locked when 0x620[0] or 0x620[1] are written When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF This counter is cleared if 0x61D,0x61E are read in the same order, after programming 0x620[1]=1

8.2.88 PRBS_STATUS_4 Register (Offset = 61Eh) [Reset = 0000h]

PRBS_STATUS_4 is shown in Table 8-92.

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Table 8-92 PRBS_STATUS_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS Checker Packet Count-2	R	0h	Holds Bits [31:16] of number of total packets received by the PRBS checker Value in register is locked when 0x620[0] or 0x620[1] are written When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF This counter is cleared if 0x61D,0x61E are read in the same order, after programming 0x620[1]=1

8.2.89 PRBS_STATUS_5 Register (Offset = 620h) [Reset = 0000h]

PRBS_STATUS_5 is shown in Table 8-93.

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Table 8-93 PRBS_STATUS_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	MAC Packet Gen Done	R	0h	Set when all MAC packets with CRC are transmitted 1b = MAC packets transmission completed 0b = MAC packet transmission in progress
11	MAC Packet Gen Busy	R	0h	1b = Packet generator is in process 0b = Packet generator is not in process
10	PRBS Checker Packet Count Overflow Status	R	0h	If PRBS Checker Packet Count overflows, this status bit is set to 1 This overflow status is cleared after clearing PRBS byte counter using 0x620[1]
9	PRBS Checker Byte Count Overflow Status	R	0h	If PRBS Checker Byte Count overflows, this status bit is set to 1 This overflow status is cleared after clearing PRBS byte counter using 0x620[1]
8	PRBS Lock	R	0h	1b = PRBS checker is locked and synced with the received stream
7-0	PRBS Error Count	R	0h	Writing 1 to bit0 locks all PRBS counters Writing 1 to bit1 locks all PRBS counters and clears the counters on read of those specific registers Bits [1:0] are self-cleared after write Reading Bits[7:0] after writing bit0/bit1, gives the number of error bits received by PRBS checker When PRBS Count Mode set to zero, count stops on 0xFF

8.2.90 PRBS_STATUS_6 Register (Offset = 622h) [Reset = 0000h]

PRBS_STATUS_6 is shown in Table 8-94.

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Table 8-94 PRBS_STATUS_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS Packer Error Count-1	R	0h	Holds Bits [15:0] of number of total packets received with error by the PRBS checker Value in register is locked when 0x620[0] or 0x620[1] are written When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF This counter is cleared if 0x622,0x623 are read in the same order, after programming 0x620[1]=1

8.2.91 PRBS_STATUS_7 Register (Offset = 623h) [Reset = 0000h]

PRBS_STATUS_7 is shown in Table 8-95.

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Table 8-95 PRBS_STATUS_7 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS Packer Error Count-2	R	0h	Holds Bits [31:16] of number of total packets received with error by the PRBS checker Value in register is locked when 0x620[0] or 0x620[1] are written When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF This counter is cleared if 0x622,0x623 are read in the same order, after programming 0x620[1]=1

8.2.92 PRBS_CTRL_4 Register (Offset = 624h) [Reset = 5511h]

PRBS_CTRL_4 is shown in Table 8-96.

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Table 8-96 PRBS_CTRL_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	MAC Packet Data	R/W	55h	Fixed data to be sent when MAC Packet Mode is set to Fixed mode
7-6	MAC Packet Mode	R/W	0h	00b = Incremental 01b = Fixed 10b = PRBS 11b = PRBS
5-3	Pattern Length in MAC Packets	R/W	2h	MAC Packets have Destination Address, Source Address, Programmed Pattern, PRBS/Fixed/Incremental Data The length of Programmed Pattern can be confgured through this register. Pattern can be programmed through 0x625,0x626,0x627 000b = 6 bytes 001b = 1 bytes 010b = 2 bytes 011b = 3 bytes 100b = 4 bytes 101b = 5 bytes 110b = 6 bytes 111b = 6 bytes
2-0	Packet Count for MAC packets Mode	R/W	1h	000b = 1 packet 001b = 10 packets 010b = 100 packets 011b = 1000 packets 100b = 10000 packets 101b = 100000 packets 110b = 1000000 packets 111b = Continuous packets

8.2.93 PATTERN_CTRL_1 Register (Offset = 625h) [Reset = 0000h]

PATTERN_CTRL_1 is shown in Table 8-97.

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Table 8-97 PATTERN_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Pattern in MAC Packets [15:0]	R/W	0h	Bytes 0,1 of programmable pattern in MAC packets

8.2.94 PATTERN_CTRL_2 Register (Offset = 626h) [Reset = 0000h]

PATTERN_CTRL_2 is shown in Table 8-98.

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Table 8-98 PATTERN_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Pattern in MAC Packets [31:16]	R/W	0h	Bytes 2,3 of programmable pattern in MAC packets

8.2.95 PATTERN_CTRL_3 Register (Offset = 627h) [Reset = 0000h]

PATTERN_CTRL_3 is shown in Table 8-99.

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Table 8-99 PATTERN_CTRL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Pattern in MAC Packets [47:32]	R/W	0h	Bytes 4,5 of programmable pattern in MAC packets

8.2.96 PMATCH_CTRL_1 Register (Offset = 628h) [Reset = 0000h]

PMATCH_CTRL_1 is shown in Table 8-100.

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Table 8-100 PMATCH_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Destination Address in MAC Packets [15:0]	R/W	0h	Destination Address field in the generated MAC packets

8.2.97 PMATCH_CTRL_2 Register (Offset = 629h) [Reset = 0000h]

PMATCH_CTRL_2 is shown in Table 8-101.

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Table 8-101 PMATCH_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Destination Address in MAC Packets [31:16]	R/W	0h	Destination Address field in the generated MAC packets

8.2.98 PMATCH_CTRL_3 Register (Offset = 62Ah) [Reset = 0000h]

PMATCH_CTRL_3 is shown in Table 8-102.

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Table 8-102 PMATCH_CTRL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Destination Address in MAC Packets [47:32]	R/W	0h	Destination Address field in the generated MAC packets

8.2.99 PKT_CRC_STAT Register (Offset = 638h) [Reset = 0000h]

PKT_CRC_STAT is shown in Table 8-103.

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Table 8-103 PKT_CRC_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	RX Bad CRC	R	0h	1b = CRC error detected in the packet received from the MDI receiver
0	TX Bad CRC	R	0h	1b = CRC error detected in the packet transmitted on MDI transmitter

8.2.100 TX_PKT_CNT_1 Register (Offset = 639h) [Reset = 0000h]

TX_PKT_CNT_1 is shown in Table 8-104.

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Table 8-104 TX_PKT_CNT_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	TX Packet Count [15:0]	R	0h	Lower 16 bits of TX packets from MAC counter Note : register is cleared when 0x639, 0x63A, 0x63B are read in sequence

8.2.101 TX_PKT_CNT_2 Register (Offset = 63Ah) [Reset = 0000h]

TX_PKT_CNT_2 is shown in Table 8-105.

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Table 8-105 TX_PKT_CNT_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	TX Packet Count [31:16]	R	0h	Upper 16 bits of TX packets from MAC counter Note : register is cleared when 0x639, 0x63A, 0x63B are read in sequence

8.2.102 TX_PKT_CNT_3 Register (Offset = 63Bh) [Reset = 0000h]

TX_PKT_CNT_3 is shown in Table 8-106.

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Table 8-106 TX_PKT_CNT_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	TX Error Packet Count	R	0h	TX packets from MAC with CRC error counter Note : register is cleared when 0x639, 0x63A, 0x63B are read in sequence

8.2.103 RX_PKT_CNT_1 Register (Offset = 63Ch) [Reset = 0000h]

RX_PKT_CNT_1 is shown in Table 8-107.

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Table 8-107 RX_PKT_CNT_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RX Packet Count [15:0]	R	0h	Lower 16 bits of RX packets received from MDI Note : register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

8.2.104 RX_PKT_CNT_2 Register (Offset = 63Dh) [Reset = 0000h]

RX_PKT_CNT_2 is shown in Table 8-108.

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Table 8-108 RX_PKT_CNT_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RX Packet Count [31:16]	R	0h	Upper 16 bits of RX packets received from MDI Note : register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

8.2.105 RX_PKT_CNT_3 Register (Offset = 63Eh) [Reset = 0000h]

RX_PKT_CNT_3 is shown in Table 8-109.

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Table 8-109 RX_PKT_CNT_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RX Error Packet Count	R	0h	Rx packet w error (CRC error) counter Note : register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

8.2.106 RMII_CTRL_1 Register (Offset = 648h) [Reset = 01X0h]

RMII_CTRL_1 is shown in Table 8-110.

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Table 8-110 RMII_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9-7	RMII Half Full Threshold	R/W	2h	FIFO Half Full Threshold in nibbles for the RMII Rx FIFO
6	RMII Enable	R/W	0h	1b = RMII Enable
5	RESERVED	R	0h	Reserved
4	RMII Follower Enable	R/W	0h	1b = RMII Follower mode is enabled Not recommended to configure this bit. Can be used as a status bit
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RMII Rev1.0 Enable	R/W	0h	1b = Enable RMII rev1.0
0	RMII Enhanced Mode Enable	R/W	0h	1b = Enable RMII Enhanced mode

8.2.107 RMII_STATUS_1 Register (Offset = 649h) [Reset = 0000h]

RMII_STATUS_1 is shown in Table 8-111.

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Table 8-111 RMII_STATUS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	RMII FIFO Empty Error	R	0h	Clear on read bit RMII fifo underflow error status
0	RMII FIFO Full Error	R	0h	Clear on Read bit RMII fifo overflow status

8.2.108 PTP_CTL Register (Offset = D00h) [Reset = 0000h]

PTP_CTL is shown in Table 8-112.

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This register provides basic controls for the PTP 802.1AS operation

Table 8-112 PTP_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12-10	Trigger Select	R/W	0h	PTP Trigger Select: This field selects the Trigger for loading control information or for enabling the Trigger. 000b = Trigger-0 001b = Trigger-1 010b = Trigger-2 011b = Trigger-3 100b = Trigger-4 101b = Trigger-5 110b = Trigger-6 111b = Trigger-7
9	Trigger Disable	R/W	0h	Disable PTP Trigger: Setting this bit disables the selected Trigger. This bit does not indicate Disable status for Triggers. Use the PTP Trigger Status register to determine Trigger Status. This bit is self-clearing and always reads back as 0. Disabling a Trigger does not disconnect it from a GPIO pin. The Trigger value is still driven to the GPIO if the Trigger is assigned to a GPIO.
8	Trigger Enable	R/W	0h	Enable PTP Trigger: Setting this bit enables the selected Trigger. This bit does not indicate Enable status for Triggers. Use the PTP Trigger Status register to determine Trigger Status. This bit is self-clearing and always reads back as 0.
7	Trigger Read	R/W	0h	Read PTP Trigger: Setting this bit begins the Trigger Read process. The Trigger is selected based on the setting of the 'Trigger Select' bits in this register. Upon setting this bit, subsequent reads of the PTP_TDR register returns the Trigger Control values. This bit is self-clearing and always reads back as 0.
6	Trigger Load	R/W	0h	Load PTP Trigger: Setting this bit disables the selected Trigger and begin the Trigger load process. The Trigger is selected based on the setting of the 'Trigger Select' bits in this register. Upon setting this bit, subsequent writes to the PTP_TDR sets the Trigger Control fields for the selected Trigger. The Trigger Load is completed after all fields have been written, or the 'Trigger Enable' bit has been set in this register. This bit is self-clearing and reads back as 0 when the Trigger Load is completed either by writing all Trigger Control fields, or by setting the Trigger Enable.
5	Read PTP Clock	WSC	0h	Read PTP Clock: Setting this bit causes the device to sample the PTP Clock time value. The time value is made available for reading through the PTP_TDR register. This bit is self-clearing and always reads back as 0.
4	Load PTP Clock	WSC	0h	Load PTP Clock: Setting this bit causes the device to load the PTP Clock time value from data previously written to the PTP_TDR register. This bit is self-clearing and always reads back as 0.
3	Step PTP Clock	R/W	0h	Step PTP Clock: Setting this bit causes the device to add a value to the PTP Clock. The value to be added is the value previously written to the PTP_TDR register. This bit is self-clearing and always reads back as 0.
2	PTP Enable	R/W	0h	Enable PTP Clock: Setting this bit enables the PTP Clock. Reading this bit returns the current enabled value. Writing a 0 to this bit has no effect.
1	PTP Disable	R/W	0h	Disable PTP Clock: Setting this bit disables the PTP Clock. Writing a 0 to this bit has no effect. This bit is self-clearing and always reads back as 0.
0	PTP Reset	R/W	0h	Reset PTP Clock: Setting this bit resets the PTP Clock and associated logic. In addition, the 802.1AS registers are reset, with the exception of the PTP_COC and PTP_CLKSRC registers. Unlike other bits in this register, this bit is not self-clearing and must be written to 0 to release the clock and logic from reset.

8.2.109 PTP_TDR Register (Offset = D01h) [Reset = 0000h]

PTP_TDR is shown in Table 8-113.

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This register provides a mechanism for reading and writing the 802.1AS Time and Trigger Control values. The function of this register is determined by controls in the PTP control register

Table 8-113 PTP_TDR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Time Data	R/W	0h	Time Data: On Reads, successively returns 16-bit values of the Clock time or Trigger Control information as selected by controls in the PTP Control register. Additional reads beyond the available fields always returns 0. On Writes, successively stores the 16-bit values of Clock time or Trigger Control Information as selected by controls in the PTP Control register.

8.2.110 PTP_STS Register (Offset = D02h) [Reset = 0000h]

PTP_STS is shown in Table 8-114.

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This register provides basic status and interrupt control for the 802.1AS PTP operation.

Table 8-114 PTP_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	TX Timestamp Ready	R	0h	Transmit Timestamp Ready: A Transmit Timestamp is available for an outbound PTP Message. This bit is cleared upon read of the Transmit Timestamp if no other timestamps are ready.
10	RX Timestamp Ready	R	0h	Receive Timestamp Ready: A Receive Timestamp is available for an inbound PTP Message. This bit is cleared upon read of the Receive Timestamp if no other timestamps are ready.
9	Trigger Done	R	0h	PTP Trigger Done: A PTP Trigger has occurred. This bit is cleared upon read. This bit is only set if Trigger Notification is turned on for the Trigger through the Trigger Configuration registers. Note that if periodic trigger is set, this interrupt does not get asserted unless the programmed trigger has resulted in a erroneous condition. If TRIG_IF_LATE bit is set, even an erroneous condition does not give out an interrupt
8	Event Ready	R	0h	PTP Event Timestamp Ready: A PTP Event Timestamp is available. This bit is cleared upon read of the PTP Event Status register if no other event timestamps are ready.
7-5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	TX Timestamp Ready Interrupt Enable	R/W	0h	Enable Transmit Timestamp Interrupt: Enable Interrupt on Transmit Timestamp Ready.
2	RX Timestamp Ready Interrupt Enable	R/W	0h	Enable Receive Timestamp Interrupt: Enable Interrupt on Receive Timestamp Ready.
1	Trigger Done Interrupt Enable	R/W	0h	Enable Trigger Interrupt: Enable Interrupt on Trigger Completion.
0	Event Ready Enable	R/W	0h	Enable Event Interrupt: Enable Interrupt on Event Timestamp Ready.

8.2.111 PTP_TSTS Register (Offset = D03h) [Reset = 0000h]

PTP_TSTS is shown in Table 8-115.

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This register provides status of the 802.1AS PTP Triggers. The bits in this register indicate the current status for each of the Trigger modules. The error bits are set if the associated notification enable (TRIG_NOTIFY) is set in the PTP Trigger Configuration Registers

Table 8-115 PTP_TSTS Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Trigger-7 Error Indication	R	0h	This bit indicates that the Trigger was improperly programmed to trigger at a time prior to the current time. This bit is cleared when the Trigger is Disabled and/ or rearmed.
14	Trigger-7 Active Status	R	0h	This bit indicates that the Trigger is enabled and has not completed.
13	Trigger-6 Error Indication	R	0h	This bit indicates that the Trigger was improperly programmed to trigger at a time prior to the current time. This bit is cleared when the Trigger is Disabled and/ or rearmed.
12	Trigger-6 Active Status	R	0h	This bit indicates that the Trigger is enabled and has not completed.
11	Trigger-5 Error Indication	R	0h	This bit indicates that the Trigger was improperly programmed to trigger at a time prior to the current time. This bit is cleared when the Trigger is Disabled and/ or rearmed.
10	Trigger-5 Active Status	R	0h	This bit indicates that the Trigger is enabled and has not completed.
9	Trigger-4 Error Indication	R	0h	This bit indicates that the Trigger was improperly programmed to trigger at a time prior to the current time. This bit is cleared when the Trigger is Disabled and/ or rearmed.
8	Trigger-4 Active Status	R	0h	This bit indicates that the Trigger is enabled and has not completed.
7	Trigger-3 Error Indication	R	0h	This bit indicates that the Trigger was improperly programmed to trigger at a time prior to the current time. This bit is cleared when the Trigger is Disabled and/ or rearmed.
6	Trigger-3 Active Status	R	0h	This bit indicates that the Trigger is enabled and has not completed.
5	Trigger-2 Error Indication	R	0h	This bit indicates that the Trigger was improperly programmed to trigger at a time prior to the current time. This bit is cleared when the Trigger is Disabled and/ or rearmed.
4	Trigger-2 Active Status	R	0h	This bit indicates that the Trigger is enabled and has not completed.
3	Trigger-1 Error Indication	R	0h	This bit indicates that the Trigger was improperly programmed to trigger at a time prior to the current time. This bit is cleared when the Trigger is Disabled and/ or rearmed.
2	Trigger-1 Active Status	R	0h	This bit indicates the Trigger is enabled and has not completed.
1	Trigger-0 Error Indication	R	0h	This bit indicates that the Trigger was improperly programmed to trigger at a time prior to the current time. This bit is cleared when the Trigger is Disabled and/ or rearmed.
0	Trigger-0 Active Status	R	0h	This bit indicates that the Trigger is enabled and has not completed.

8.2.112 PTP_RATEL Register (Offset = D04h) [Reset = 0000h]

PTP_RATEL is shown in Table 8-116.

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This register contains the low 16-bits of the PTP Rate control. The PTP Rate Control indicates a positive or negative adjustment to the reference clock period in units of 2^-32 ns. On each reference clock cycle, the PTP Clock is adjusted by adding ref_clk_period +/- PTP_Rate. Write the PTP Rate as PTP_RATEH, followed by PTP_RATEL. The rate takes effect on the write to the PTP_RATEL register

Table 8-116 PTP_RATEL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP Rate Control Low	R/W	0h	PTP Rate Control Low 16-bits: Writing to this register sets the low 16-bits of the Rate Control value. The Rate Control value is in units of 2^-32 ns. Upon writing to this register, the full Rate Control value is loaded to the device.

8.2.113 PTP_RATEH Register (Offset = D05h) [Reset = 0000h]

PTP_RATEH is shown in Table 8-117.

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This register contains the upper 10-bits of the 26-bit PTP Rate control. In addition, it contains a direction control to indicate whether the device is operating faster or slower than the reference clock frequency. When setting the PTP Rate, write this register first, followed by a write to the PTP_RATEL register. The rate takes effect on the write to the PTP_RATEL register.

Table 8-117 PTP_RATEH Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PTP Rate Direction	R/W	0h	The setting of this bit controls whether the device operates at a higher or lower frequency than the reference clock. 0h = The PTP RATE value is added to the clock on every cycle indicating Lower Frequency 1h = The PTP RATE value is subtracted from the clock on every cycle indicating Higher Frequency
14	Temporary Rate Enable	R/W	0h	PTP Temporary Rate: Setting this bit causes the rate to be applied to the clock for the duration set in the PTP Temporary Rate Duration register (PTP_TRD). 0h = Normal Rate 1h = Temporary Rate
13-10	RESERVED	R	0h	Reserved
9-0	PTP Rate Control High	R/W	0h	PTP Rate Control High 10-bits: Writing to this register sets the high 10-bits of the Rate Control value. The Rate Control value is in units of 2^-32 ns.

8.2.114 PTP_TXTS Register (Offset = D08h) [Reset = 0000h]

PTP_TXTS is shown in Table 8-118.

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This register provides a mechanism for reading the Transmit Timestamp. The fields are read in the following order:
Timestamp_ns [15:0];

Overflow_cnt[1:0], Timestamp_ns[29:16];

Timestamp_sec[15:0],

Timestamp_sec[31:16]

The Overflow_cnt value indicates if timestamps were dropped due to an overflow of the Transmit Timestamp queue. The overflow counter sticks at a value of three if additional timestamps were missed.

Note:
Each Transmit Timestamp information consists of Four reads. TXTS_RDY status (0xD02, Bit-11) is required to be read to access the next available Transmit Timestamp information.

Table 8-118 PTP_TXTS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP TX Timestamp	R	0h	PTP Transmit Timestamp: Reading this register returns the Transmit Timestamp in four 16-bit reads.

8.2.115 PTP_RXTS Register (Offset = D09h) [Reset = 0000h]

PTP_RXTS is shown in Table 8-119.

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This register provides a mechanism for reading the Receive Timestamp and identification information. The fields are read in the following order:
Timestamp_ns [15:0]

Overflow_cnt[1:0], Timestamp_ns[29:16]

Timestamp_sec[15:0]

Timestamp_sec[31:16]

sequenceId[15:0]

messageType[3:0], source_hash[11:0]

The Overflow_cnt value indicates if timestamps were dropped due to an overflow of the Transmit Timestamp queue. The overflow counter sticks at a value of three if additional timestamps were missed.

Note:
Each Receive Timestamp information consists of Six reads. RXTS_RDY status (0xD02, Bit-12) is required to be read to access the next available Receive Timestamp information.

Table 8-119 PTP_RXTS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP RX Timestamp	R	0h	PTP Receive Timestamp: Reading this register returns the Receive Timestamp and identification information in successive 16-bit reads.

8.2.116 PTP_ESTS Register (Offset = D0Ah) [Reset = 0000h]

PTP_ESTS is shown in Table 8-120.

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This register provides Status for the Event Timestamp unit. Reading this register provides status for the next Event Timestamp contained in the Event Data Register. If this register is 0, no Event Timestamp is available in the Event Data Register. Reading this register automatically moves to the next Event in the queue.

Table 8-120 PTP_ESTS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10-8	Events Missed Counter	R	0h	Number of Events Missed: Indicates number of events have been missed prior to this timestamp for the EVNT_NUM indicated. This count value sticks at 7 if more than 7 events are missed.
7-6	Event Timestamp Change Length	R	0h	Event Timestamp Length: Indicates length of the Timestamp field in 16-bit words minus 1. Although all fields are available, this indicates how many of the fields contain data different from the previous Event Timestamp. This allows software to avoid reading more significant fields if they have not changed since the previous timestamp. This field is valid for both single and multiple events. The following shows the number of least significant fields which have new data for each setting 0h = One 16-bit field is new (Timestamp_ns[15:0]) 1h = Two 16-bit fields are new 2h = Three 16-bit fields are new 3h = All four 16-bit fields are new
5	Event Edge Detected	R	0h	Event edge configuration: Indicates whether the event is a rise or falling event. If the 'Multiple Event Detected' bit is set to 1, this bit indicates the Rise/Fall direction for the event indicated by EVNT_NUM. 0h = Falling edge detected 1h = Rising edge detected
4-2	Event Number Detected	R	0h	Event Number: Indicates Event Timestamp Unit which detected an event. If the 'Multiple Event Detected' bit is 1, this indicates the lowest event number captured. If events have been missed prior to this timestamp, it indicates the lowest event number captured which had at least one missed event.
1	Multiple Events Detected	R	0h	Multiple Event Detect: Indicates multiple events were detected at the same time. If multiple events are detected, an extended event status field is available as the first data read from the Event Data register. 0h = Single event detected 1h = Multiple events detected
0	PTP Event Detected	R	0h	Indicates an Event has been detected by one of the Event Timestamp Units

8.2.117 PTP_TRIG Register (Offset = D10h) [Reset = 0000h]

PTP_TRIG is shown in Table 8-121.

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This register provides basic configuration for IEEE 802.1AS Triggers. To write configuration to a trigger, set the TRIG_WR bit along with the TRIG_SEL and other control information. To read configuration from a trigger, set the TRIG_SEL encoding to the trigger desired, and set the TRIG_WR bit to 0. The subsequent read of the PTP_TRIG register returns the configuration information.

Note:
A Pulse is seen in case toggle trigger is set with trig_if_late condition.
In trig_if_late condition, pulse trigger doesnt give pulse of the configured width.

Table 8-121 PTP_TRIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Trigger Pulse Select	R/W	0h	Trigger Pulse: Setting this bit causes the trigger to generate a pulse rather than a single rising or falling edge.
14	Trigger Periodic Enable	R/W	0h	Trigger Periodic: Setting this bit causes the trigger to generate a periodic signal. If this bit is 0, the trigger generates a single Pulse or Edge depending on the Trigger Control settings.
13	Trigger If Late	R/W	0h	Trigger-if-late Control: Setting this bit allows an immediate trigger in the event the trigger is programmed to a time value which is less than the current time. This provides a mechanism for generating an immediate trigger or to immediately begin generating a periodic signal. For a periodic signal, no notification is generated if this bit is set and a late trigger occurs. Only use this function for Trigger 0 or Trigger 1. This bit has to be programmed before loading the trigger (loading the timestamp).
12	Trigger Notification Enable	R/W	0h	Trigger Notification Enable: Setting this bit enables trigger status to be reported on completion of a trigger or on an error detection due to late trigger. If trigger interrupts are enabled, the notification also results in an interrupt being generated.
11-8	Trigger GPIO Select	R/W	0h	GPIO trigger output configuration: Setting this field to a non-zero value connects the trigger to the associated GPIO pin. 0h = No GPIO is selected 1h = LED_0 2h = LED_1 3h = RX_ER 4h = CLKOUT 5h = GPIO_3 6h = GPIO_4 7h = GPIO_5
7	Trigger Toggle Mode	R/W	0h	Trigger Toggle mode enable: Setting this bit puts the trigger into toggle mode. In toggle mode, the initial value is ignored and the trigger output is toggled at the trigger time.
6-4	RESERVED	R	0h	Reserved
3-1	Trigger Select	R/W	0h	Trigger Configuration Select: This field selects the trigger for configuration read or write.
0	Trigger Configuration Write	R/W	0h	Trigger Configuration Write: Setting this bit generates a Configuration Write to the selected trigger. This bit is self-clear bit and always reads back as 0.

8.2.118 PTP_EVNT Register (Offset = D11h) [Reset = 0000h]

PTP_EVNT is shown in Table 8-122.

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This register provides basic configuration for IEEE 802.1AS Events. To write configuration to an Event Timestamp Unit, set the EVNT_WR bit along with the EVNT_SEL and other control information. To read configuration from an Event Timestamp Unit, set the EVNT_SEL encoding to the Event desired, and set the EVNT_WR bit to 0. The subsequent read of the PTP_EVNT register returns the configuration information.

Table 8-122 PTP_EVNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	Event Rise Detect Enable	R/W	0h	Event Rise Detect Enable: Enable detection of a rising edge transition on the selected event input.
13	Event Fall Detect Enable	R/W	0h	Event Fall Detect Enable: Enable detection of a falling edge transition on the selected event input.
12	Single Event Capture	R/W	0h	Single Event Capture: Setting this bit to a 1 enables single event capture operation. The EVNT_RISE and EVNT_FALL are cleared upon a valid event timestamp capture.
11-8	Event GPIO Select	R/W	0h	GPIO event capture configuration: Setting this field to a non-zero value connects the event to the associated GPIO pin. This field can also be used to capture events based on trigger outputs or AVB clock outputs 0h = No GPIO is selected 1h = LED_0 2h = LED_1 3h = RX_ER 4h = CLKOUT 5h = GPIO_3 6h = GPIO_4 7h = GPIO_5 8h = Media Clock 9h = Codec Clock Ah = Bit Clock Bh = Trigger 0 Ch = Trigger 1
7-4	RESERVED	R	0h	Reserved
3-1	Event Select	R/W	0h	Event Select: This field selects the Event Timestamp Unit for configuration read or write. 000b = Event-0 001b = Event-1 010b = Event-2 011b = Event-3 100b = Event-4 101b = Event-5 110b = Event-6 111b = Event-7
0	Event Configuration Write	R/W	0h	Event Configuration Write: Setting this bit generates a Configuration Write to the selected Event Timestamp Unit.

8.2.119 PTP_TXCFG0 Register (Offset = D12h) [Reset = 0000h]

PTP_TXCFG0 is shown in Table 8-123.

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This register provides configuration for IEEE 802.1AS Transmit Timestamp operation.

Table 8-123 PTP_TXCFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Sync Message One-Step Enable	R/W	0h	Sync Message One-Step Enable: Enable automatic insertion of timestamp into transmit Sync Messages. Device automatically parses message and insert the timestamp in the correct location. UDP checksum and CRC fields is regenerated.
14	TX TimeStamp Info Enable	R/W	0h	Enable latching of message type, hash value, sequence id along with Timestamp for transmit event packets and transmit these fields through PSF
13	Insert Delay Request	R/W	0h	Insert Delay_Req timestamp in Delay_Resp: If this bit is set to a 1, the device inserts the timestamp for transmitted Delay_Req messages into inbound Delay_Resp messages. The most recent timestamp is used for any inbound Delay_Resp message. The receive timestamp insertion logic must be enabled through the PTP Receive Configuration registers.
12	NTP Timestamp Enable	R/W	0h	Enable Timestamping of NTP Packets: If this bit is set to 0, the device checks the UDP protocol field for a PTP Event message (value 319). If this bit is set to 1, the device checks the UDP protocol field for an NTP message (value 123). This setting applies to the transmit and receive packet parsing engines.
11	Ignore Two-Step Flag	R/W	0h	Ignore Two_Step flag for One-Step operation: If this bit is set to a 0, the device does not insert a timestamp if the Two_Step bit is set in the flags field of the PTP header. If this bit is set to 1, the device inserts a timestamp independent of the setting of the Two_Step flag.
10	Disable CRC One-Step	R/W	0h	Disable checking of CRC for One-Step operation: If this bit is set to a 0, the device forces a CRC error for One-Step operation if the incoming frame has a CRC error. If this bit is set to a 1, the device sends the One-Step frame with a valid CRC, even if the incoming CRC is invalid.
9	Checksum Correction One-Step	R/W	0h	Enable UDP Checksum correction for One-Step Operation: Enables correction of the UDP checksum for messages which include insertion of the timestamp. The checksum is corrected by modifying the last two bytes of the UDP data. The last two bytes must be transmitted by the MAC as 0s. This control must be set for proper IPv6/UDP One-Step operation. This control has no effect for Layer2 Ethernet messages.
8	IP Address Filter	R/W	0h	Enable IEEE 802.1AS defined IP address filter: Enable filtering of UDP/IP Event messages using the IANA assigned IP Destination addresses. If this bit is set to 1, packets with IP Destination addresses which do not match the IANA assigned addresses is not timestamped. This field affects operation for both IPv4 and IPv6. If this field is set to 0, IP destination addresses is ignored.
7	Layer2 Timestamp Enable	R/W	0h	Layer2 Timestamp Enable: Enables detection of IEEE 802.3/Ethernet encapsulated PTP event messages.
6	IPv6 Timestamp Enable	R/W	0h	IPv6 Timestamp Enable: Enables detection of UDP/IPv6 encapsulated PTP event messages.
5	IPv4 Timestamp Enable	R/W	0h	IPv4 Timestamp Enable: Enables detection of UDP/IPv4 encapsulated PTP event messages.
4-1	PTP Version	R/W	0h	PTP Version: Enable Timestamp capture for a specific version of the IEEE 802.1AS specification. This field can be programmed to any value between 1 and 15 and allows support for future versions of the IEEE 802.1AS specification. A value of 0 disables version checking (not recommended).
0	Transmit Timestamp Enable	R/W	0h	Transmit Timestamp Enable: Enable Timestamp capture for Transmit.

8.2.120 PTP_TXCFG1 Register (Offset = D13h) [Reset = 0000h]

PTP_TXCFG1 is shown in Table 8-124.

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This register provides data and mask fields to filter the first byte in a PTP Message. This function is disabled if all the mask bits are set to 0.

Table 8-124 PTP_TXCFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	Transmit Byte0 Mask	R/W	0h	Byte0 Mask: Bit mask to be used for matching Byte0 of the PTP Message. A one in any bit enables matching for the associated data bit. If no matching is required, set all bits of the mask to 0
7-0	Transmit Byte0 Data	R/W	0h	Byte0 Data: Data to be used for matching Byte0 of the PTP Message.

8.2.121 PSF_CFG0 Register (Offset = D14h) [Reset = 4700h]

PSF_CFG0 is shown in Table 8-125.

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This register provides configuration for the Phy Status Frame function.

Table 8-125 PSF_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	PSF Termination Field Addition Enable	R/W	1h	1b = Enable addition of termination field for PSF packets
13	RESERVED	R	0h	Reserved
12-11	PSF MAC Source Address	R/W	0h	Phy Status Frame Mac Source Address: 0h = Use Mac Address [08 00 17 0B 6B 0F] 1h = Use Mac Address [08 00 17 00 00 00] 2h = Use Mac Multicast Dest Address 3h = Use Mac Address [00 00 00 00 00 00]
10-8	PSF Minimum Preamble	R/W	7h	Phy Status Frame minimum preamble: Determines the minimum preamble bytes required for sending packets on the MII interface. TI recommends that this be set to the smallest value the MAC tolerates.
7	PSF Endian Control	R/W	0h	Phy Status Frame Endian control: For each 16-bit field in a Status Message, the data is normally be presented in network byte order (Most significant byte first). If this bit is set to a 1, the byte data fields is reversed so that the least significant byte is first.
6	PSF Packet Type	R/W	0h	This bit controls the type of packet used for Phy Status Frames: 0h = Layer2 Ethernet packets 1h = IPv4 packets.
5	PSF Delivery Enable	R/W	0h	Phy Control Frame Read Phy Status Frame enable: Enable Phy Status Frame delivery of Phy Control Frame read data. Data read through a Phy Control Frame returns in a Phy Status Frame.
4	PSF Error Delivery Enable	R/W	0h	PSF Error Phy Status Frame enable: Enable Phy Status Frame delivery of Phy Status Frame Errors. This bit does not independently enable Phy Status Frame operation. One of the other enable bits must be set for Phy Status Frames to be generated.
3	PSF TX Timestamp Enable	R/W	0h	Transmit Timestamp Phy Status Frame enable: Enable Phy Status Frame delivery of Transmit Timestamps.
2	PSF RX Timestamp Enable	R/W	0h	Receive Timestamp Phy Status Frame enable: Enable Phy Status Frame delivery of Receive Timestamps.
1	PSF Trigger Enable	R/W	0h	Trigger Phy Status Frame enable: Enable Phy Status Frame delivery of Trigger Status.
0	PSF Event Enable	R/W	0h	Event Phy Status Frame enable: Enable Phy Status Frame delivery of Event Timestamps.

8.2.122 PTP_RXCFG0 Register (Offset = D15h) [Reset = 0000h]

PTP_RXCFG0 is shown in Table 8-126.

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This register provides configuration for IEEE 802.1AS Receive Timestamp operation.

Table 8-126 PTP_RXCFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Domain Match Enable	R/W	0h	Domain Match Enable: If set to 1, the Receive Timestamp unit requires the domain Number field (octet 4) of the PTP Header to match the value programmed in the PTP_DOMAIN field of the PTP_RXCFG3 register. If set to 0, the Receive Timestamp ignores the PTP_DOMAIN field.
14	Alternate Leader Timestamp Enable	R/W	0h	Alternate Leader Timestamp Disable: Disables Timestamp generation if the Alternate_Leader flag is set. 0h = Ignore Alternate_Leader flag 1h = Do not generate Timestamp if Alternate_Leader is 1
13	IP Address Data Select	R/W	0h	IP Address data select: Selects portion of IP address accessible through the PTP_RXCFG2 register. 0h = Two Most Significant Octets 1h = Two Least Significant Octets
12	User Programmed IP Address Filter Enable	R/W	0h	Enable User-programmed IP address filter: Enable detection of UDP/IP Event messages using a programmable IP address. The IP Address is set using the PTP_RXCFG2 register.
11	PTP Receive Follower Only	R/W	0h	Receive Follower Only: By default, the Receive Timestamp Unit provides Timestamps for event messages meeting other requirements. Setting this bit to a 1 prevents Delay_Req messages from being Timestamped by requiring that the Control Field (offset 32 in the PTP message) be set to a value other than 1.
10-8	IP Address Filters Enable	R/W	0h	Enable IEEE 802.1AS defined IP address filters: Enable detection of UDP/IP Event messages using the IANA assigned IP Destination addresses. This field affects operation for both IPv4 and IPv6. A Timestamp is captured for the PTP message if the IP destination address matches the following: bxx1 : Dest IP address is 224.0.1.129 bx1x : Dest IP address is 224.0.1.130 - 132 b1xx : Dest IP address is 224.0.0.107
7	L2 Timetamp Enable	R/W	0h	Layer2 Timestamp Enable: Enables detection of IEEE 802.3/Ethernet encapsulated PTP event messages.
6	IPv6 Timestamp Enable:	R/W	0h	IPv6 Timestamp Enable: Enables detection of UDP/IPv6 encapsulated PTP event messages.
5	IPv4 Timestamp Enable:	R/W	0h	IPv4 Timestamp Enable: Enables detection of UDP/IPv4 encapsulated PTP event messages.
4-1	RX PTP Version	R/W	0h	PTP Version: Enable Timestamp capture for a specific version of the IEEE 802.1AS specification. This field can be programmed to any value between 1 and 15 and allows support for future versions of the IEEE 802.1AS specification. A value of 0 disables version checking (not recommended).
0	Receive Timestamp Enable	R/W	0h	Receive Timestamp Enable: Enable Timestamp capture for Receive.

8.2.123 PTP_RXCFG1 Register (Offset = D16h) [Reset = 0000h]

PTP_RXCFG1 is shown in Table 8-127.

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This register provides data and mask fields to filter the first byte in a PTP Message. This function is disabled if all the mask bits are set to 0.

Table 8-127 PTP_RXCFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	Receive Byte0 Mask	R/W	0h	Byte0 Mask: Bit mask to be used for matching Byte0 of the Receive PTP Message. A one in any bit enables matching for the associated data bit. If no matching is required, set all bits of the mask to 0.
7-0	Receive Byte0 Data	R/W	0h	Byte0 Data: Data to be used for matching Byte0 of the Receive PTP Message.

8.2.124 PTP_RXCFG2 Register (Offset = D17h) [Reset = 0000h]

PTP_RXCFG2 is shown in Table 8-128.

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This register provides for programming an IP address to be used for filtering packets to detect PTP Event Messages. Since the IPv4 address is 32-bits, to write an IP address, software must write two 16-bit values. The USER_IP_SEL bit in the PTP_RXCFG0 register selects which octect of the IP address are accessible through this register.

For example, to write an IP address of 224.0.1.129, software must do the following:

1. Set USER_IP_SEL bit in PTP_RXCFG0 register to 0

2. Write 0xE000 (224.00) to PTP_RXCFG2

3. Set USER_IP_SEL bit in the PTP_RXCFG0 register to 1

4. Write 0x0181 (01.129) to PTP_RXCFG2

Reading this register returns the IP address field selected by USER_IP_SEL.

Table 8-128 PTP_RXCFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Receive IP Address Data	R/W	0h	Receive IP Address Data: 16-bits of the IP Address field to be read or written. The 'IP Address Data Select' bit in the PTP_RXCFG0 register selects the portion of the IP address is to be read or written. - 'IP Address Data Select' in RX_CFG0 == 0 -> set MSB 2 bytes of IPv4/IPv6 Addr in PTP_RXCFG2 register in the normal byte format. - 'IP Address Data Select' in RX_CFG0 == 1 -> set LSB 2 bytes of IPv4/IPv6 Address in PTP_RXCFG2 register in the normal byte format. When IPv4, the complete ip address can be set, when IPv6 only MSB 2 bytes of the 16 byte address and LSB 2 bytes of the 16 byte address are compared.

8.2.125 PTP_RXCFG3 Register (Offset = D18h) [Reset = C000h]

PTP_RXCFG3 is shown in Table 8-129.

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This register provides extended configuration for IEEE 802.1AS Receive Timestamp operation.

Table 8-129 PTP_RXCFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RX Minimum IFG after Timestamp	R/W	Ch	Minimum Inter-frame Gap: When a Timestamp is appended to a PTP Message, the length of the packet can get extended. This could reduce the Inter-frame Gap (IFG) between packets by as much as 8-byte times (6400 ns at 10 Mb, 640 ns at 100 Mb, 64 ns at 1G). This field sets a minimum on the IFG between packets in number of byte times. If the IFG is set larger than the actual IFG, Preamble bytes of the subsequent packet gets dropped. Set this value to the lowest possible value that the attached MAC can support.
11	Timestamp on Checksum Error	R/W	0h	Record Timestamp if UDP Checksum Error: By default, Timestamps is discarded for packets with UDP Checksum errors. If this bit is set, the Timestamp is made available in the normal manner.
10	Timestamp on CRC Error	R/W	0h	Record Timestamp if CRC Error: By default, Timestamps is discarded for packets with CRC errors. If this bit is set, the Timestamp is made available in the normal manner.
9	RESERVED	R	0h	Reserved
8	Insert Timestamp	R/W	0h	Enable Timestamp Insertion: Enables Timestamp insertion into a packet containing a PTP Event Message. If this bit is set, the Timestamp does not available through the PTP Receive Timestamp register.
7-0	PTP Domain Matching Value	R/W	0h	PTP Domain Value: Value of the PTP Message domainNumber field. If PTP_RXCFG0:DOMAIN_EN is set to 1, the Receive Timestamp unit only captures a Timestamp if the domainNumber in the receive PTP message matches the value in this field. If the DOMAIN_EN bit is set to 0, the domainNumber field is ignored.

8.2.126 PTP_RXCFG4 Register (Offset = D19h) [Reset = 0000h]

PTP_RXCFG4 is shown in Table 8-130.

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This register provides extended configuration for IEEE 802.1AS Receive Timestamp operation. Disable Timestamp insertion using (through PTP_RXCFG3[8]) prior to changing any of the fields in this register.

Table 8-130 PTP_RXCFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	IPV4 UDP Checksum Modify	R/W	0h	Enable IPV4 UDP modification: When timestamp insertion is enabled, this bit controls how UDP checksums are handled for IPV4 PTP event messages. If set to a 0, the device clears the UDP checksum. If a UDP checksum error is detected the device forces a CRC error. If set to a 1, the device does not clear the UDP checksum. Instead it generates a 2-byte value to correct the UDP checksum and append this immediately following the PTP message. If an incoming UDP checksum error is detected, the device causes a UDP checksum error in the modified field. Only use this function if the incoming packets contain two extra bytes of UDP data following the PTP message. Do not enable this for systems using version 1 of the IEEE 802.1AS specification.
14	Seconds Timestamp Enable	R/W	0h	Enable Timestamp Seconds: Setting this bit to a 1 enables inserting a seconds field when Timestamp Insertion is enabled. If set to 0, only the nanoseconds portion of the Timestamp is inserted in the packet. This bit is ignored if 'Insert Timestamp' is 0. This bit is applicable for insertion of timestamps into PTP.
13-12	Seconds Timestamp Length	R/W	0h	Inserted Timestamp Seconds Length: For a PTP message, this field indicates the length of the Seconds field to be inserted in the PTP message. This field is ignored if 'Insert Timestamp' is 0 or if TS_SEC_EN is 0. 0h = Least Significant Byte only of Seconds field 1h = Two Least Significant Bytes of Seconds field 2h = Three Least Significant Bytes of Seconds field 3h = All four Bytes of Seconds field
11-6	RX Timestamp nanosec Field Offset	R/W	0h	Receive Timestamp Nanoseconds offset: This field provides an offset to the Nanoseconds field when inserting a Timestamp into a received PTP message. The offset indicates the byte offset from the beginning of the PTP message. This field is ignored if 'Insert Timestamp' is 0.
5-0	RX Timestamp sec Field Offset	R/W	0h	Receive Timestamp Seconds offset: This field provides an offset to the Seconds field when inserting a Timestamp into a received PTP message. The offset indicates the byte offset from the beginning of the PTP message. This field is ignored if 'Insert Timestamp' is 0.

8.2.127 PTP_TRDL Register (Offset = D1Ah) [Reset = 0000h]

PTP_TRDL is shown in Table 8-131.

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This register contains the low 16-bits of the duration in clock cycles to use the Temporary Rate as programmed in the PTP_RATEH and PTP_RATEL registers. Since the Temporary Rate takes affect upon writing the PTP_RATEL register, program this register before setting the Temporary Rate. This register does not need to be reprogrammed for each use of the Temporary Rate registers.

Table 8-131 PTP_TRDL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Temporary Rate Duration [15:10]	R/W	0h	PTP Temporary Rate Duration Low 16-bits: This register sets the duration for the Temporary Rate in number of clock cycles. The actual Time duration is dependent on the value of the Temporary Rate.

8.2.128 PTP_TRDH Register (Offset = D1Bh) [Reset = 0000h]

PTP_TRDH is shown in Table 8-132.

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This register contains the high 10-bits of the duration in clock cycles to use the Temporary Rate as programmed in the PTP_RATEH and PTP_RATEL registers. Since the Temporary Rate takes affect upon writing the PTP_RATEL register, program this register before setting the Temporary Rate. This register does not need to be reprogrammed for each use of the Temporary Rate registers.

Table 8-132 PTP_TRDH Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	Temporary Rate Duration [25:16]	R/W	0h	PTP Temporary Rate Duration High 10-bits: This register sets the duration for the Temporary Rate in number of clock cycles. The actual Time duration is dependent on the value of the Temporary Rate.

8.2.129 PTP_EVNT_TSU_CFG Register (Offset = D1Ch) [Reset = 0002h]

PTP_EVNT_TSU_CFG is shown in Table 8-133.

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This register provides configuration of storage of Event Timestamps and the transmission to Host using PSF

Table 8-133 PTP_EVNT_TSU_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	Full Trigger Timestamp Storage Enable	R/W	1h	1b = Enable storing of full timestamp for triggers independent of the change from the previous event timestamp
0	Full Event Timestamp Storage Enable	R/W	0h	1b = Enable storing of full timestamp for events independent of the change from the previous event timestamp

8.2.130 PSF_TRIG_TS_EN Register (Offset = D1Dh) [Reset = 0000h]

PSF_TRIG_TS_EN is shown in Table 8-134.

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This register enables PHY Status Frame delivery of timestamp corresponding to edges of the generated trigger.

Table 8-134 PSF_TRIG_TS_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	Trigger Timestamp PHY Status Frame Enable	R/W	0h	This enables PHY Status Frame delivery of timestamp corresponding to edges of the generated trigger. Every bit corresponds to an enable for 1 trigger unit as: 8'b00000001: Enables PSF delivery for trigger0 edge timestamp 8'b00000010: Enables PSF delivery for trigger1 edge timestamp 8'b00000100: Enables PSF delivery for trigger2 edge timestamp 8'b00001000: Enables PSF delivery for trigger3 edge timestamp 8'b00010000: Enables PSF delivery for trigger4 edge timestamp 8'b00100000: Enables PSF delivery for trigger5 edge timestamp 8'b01000000: Enables PSF delivery for trigger6 edge timestamp 8'b10000000: Enables PSF delivery for trigger7 edge timestamp

8.2.131 PTP_COC Register (Offset = D20h) [Reset = 000Ah]

PTP_COC is shown in Table 8-135.

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This register provides configuration for the PTP clock-synchronized output divide-by-N clock.

Table 8-135 PTP_COC Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	PTP Clock Output Division Value	R/W	Ah	PTP Clock output Divide-by Value: This field sets the divide-by value for the 802.1AS sync output clock. The 802.1AS sync clock output is derived by dividing output clock of PTP_PLL. Valid values range from 2 to 255 (0x02 to 0xFF), giving a nominal output frequency range of 125 MHz down to 980.4 kHz. Divide-by values of 0 and 1 are not valid and stops the output clock.

8.2.132 PSF_CFG1 Register (Offset = D21h) [Reset = 0000h]

PSF_CFG1 is shown in Table 8-136.

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This register provides configuration for the Phy Status Frame function. Specifically, the 16-bit value in this register is used as the first 16-bits of the PTP Header data for the Phy Status Frame.

Table 8-136 PSF_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	PTP v2 reserved field: This field contains the reserved 4-bit field (at offset 1) to be sent in status packets from the Phy to the local MAC using the MII receive data interface.
11-8	PTP Version Field	R/W	0h	PTP v2 versionPTP field: This field contains the versionPTP field to be sent in status packets from the Phy to the local MAC using the MII receive data interface.
7-4	PTP TransportSpecific Field	R/W	0h	PTP v2 Header transportSpecific field: This field contains the transportSpecific field to be sent in status packets from the Phy to the local MAC using the MII receive data interface.
3-0	PTP Message Type Field	R/W	0h	PTP v2 messageType field: This field contains the messageType field to be sent in status packets from the Phy to the local MAC using the MII receive data interface.

8.2.133 PSF_CFG2 Register (Offset = D22h) [Reset = 0000h]

PSF_CFG2 is shown in Table 8-137.

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This register provides configuration for the Phy Status Frame function. Specifically, the 16-bit value in this register is used as the first 16-bits of the IP Source address for an IPv4 Phy Status Frame.

Table 8-137 PSF_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	IP Source Address 1	R/W	0h	Second byte of IP source address: This field contains the second byte of the IP source address.
7-0	IP Source Address 0	R/W	0h	First byte of IP source address: This field contains the most significant byte of the IP source address.

8.2.134 PSF_CFG3 Register (Offset = D23h) [Reset = 0000h]

PSF_CFG3 is shown in Table 8-138.

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This register provides configuration for the Phy Status Frame function. Specifically, the 16-bit value in this register is used as the second 16-bits of the IP Source address for an IPv4 Phy Status Frame.

Table 8-138 PSF_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	IP Source Address 3	R/W	0h	Fourth byte of IP source address: This field contains the fourth byte of the IP source address.
7-0	IP Source Address 2	R/W	0h	Third byte of IP source address: This field contains the third byte of the IP source address.

8.2.135 PSF_CFG4 Register (Offset = D24h) [Reset = 0000h]

PSF_CFG4 is shown in Table 8-139.

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This register provides configuration for the Phy Status Frame function. Specifically, the 16-bit value in this register is used to assist in computation of the IP checksum for an IPv4 Phy Status Frame.

Table 8-139 PSF_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	IP Checksum	R/W	0h	IP Checksum: This field contains a precomputed value of ones-complement addition of all fixed values in the IP Header. The device adds the Total Length and Identification values to generate the final checksum.

8.2.136 PTP_INTCTL Register (Offset = D26h) [Reset = 0000h]

PTP_INTCTL is shown in Table 8-140.

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This register provides configuration for the IEEE 802.1AS interrupt function, allowing the PTP Interrupt to use any of the GPIO pins.

Table 8-140 PTP_INTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3-0	PTP Interrupt GPIO Select	R/W	0h	PTP Interrupt GPIO select: To enable interrupts on a GPIO pin, set this field to the required GPIO. 0h = INT_N 1h = LED_0 2h = LED_1 3h = RX_ER 4h = CLKOUT 5h = GPIO_3 6h = GPIO_4 7h = GPIO_5

8.2.137 PTP_CLKSRC Register (Offset = D27h) [Reset = 0084h]

PTP_CLKSRC is shown in Table 8-141.

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This register provides configuration for the reference clock source driving the IEEE 802.1AS hardware logic. The source clock period is also used by the 802.1AS nanoseconds clock adder to add the proper value every reference clock cycle.

Table 8-141 PTP_CLKSRC Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	PTP Clock Reference Select-1	R/W	0h	PTP Clock Source Select: Selects among possible sources for the PTP reference clock Mapping of {PTP Clock Reference Select-1, PTP Clock Reference Select-2} is as follows: b1000 : External reference from LED_0 b1010 : External reference from GPIO_5 b0000 : PLL 250M b0100 : PLL 125M b0010 : Clock from PTP_PLL b0001 : Recovered 200M b0101 : Recovered 100M
13	PTP Ref Clock Division Enable	R/W	0h	Clock division enable: If set to 1, enables division of the PTP reference clock by a factor of value programmed in CLK_DIV_VAL.
12-11	PTP Clock Reference Select-2	R/W	0h	PTP Clock Source Select: Selects among possible sources for the PTP reference clock Mapping of {PTP Clock Reference Select-1, PTP Clock Reference Select-2} is as follows: b1000 : External reference from LED_0 b1010 : External reference from GPIO_5 b0000 : PLL 250M b0100 : PLL 125M b0010 : Clock from PTP_PLL b0001 : Recovered 200M b0101 : Recovered 100M
10-7	PTP Ref Clock Division Value	R/W	1h	Clock division divider value: When the clock source selection is the Divide-by-N using 'PTP Ref Clock Division Enable', these bits are used as the N value.
6-0	PTP Clock Source Period	R/W	4h	PTP Clock Source Period: This field configures the PTP clock source period in nanoseconds. Program the clock source period as > 2

8.2.138 PTP_ETYPE Register (Offset = D28h) [Reset = F788h]

PTP_ETYPE is shown in Table 8-142.

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This register provides the Ethernet Type (Ethertype) field for PTP transport over Ethernet (Layer2).

Table 8-142 PTP_ETYPE Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP EtherType	R/W	F788h	PTP EtherType: This field contains the Ethernet Type field used to detect PTP messages transported over Ethernet layer 2. Program this register in reverse byte format. For example, the ethertype expected from PTP packets is 0x88F7 so 0xF788 is made as default value.

8.2.139 PTP_OFF Register (Offset = D29h) [Reset = 0000h]

PTP_OFF is shown in Table 8-143.

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This register provides the byte offset to the PTP message in a Layer2 Ethernet frame.

Table 8-143 PTP_OFF Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	PTP Message Field Offset	R/W	0h	PTP Message Offset: This field contains the offset in bytes to the PTP Message from the preceding header. For Layer2, this the offset from the Ethernet Type Field. For UDP/IP, it is the offset from the end of the UDP Header.

8.2.140 PTP_RXHASH Register (Offset = D2Bh) [Reset = 0000h]

PTP_RXHASH is shown in Table 8-144.

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This register provides configuration for the source identity hash filter of the PTP receive packet parser. If enabled, the receive parse logic delivers a receive timestamp only if the hash function on the ten octet sourcePortIdentity field correctly matches the programmed value. The source identity hash filter does not affect timestamp insertion.

Table 8-144 PTP_RXHASH Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	Receive Hash Enable	R/W	0h	Receive Hash Enable: Enables filtering of PTP messages based on the hash function on the ten octet sourcePortIdentity field.
11-0	Receive Hash	R/W	0h	Receive Hash: This field contains the expected source identity hash value for incoming PTP event messages.

8.2.141 PTP_EVENT_GPIO_SEL Register (Offset = D30h) [Reset = 0000h]

PTP_EVENT_GPIO_SEL is shown in Table 8-145.

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This register provides controls to make which IOs as inputs to enable event timestamping on them.

Table 8-145 PTP_EVENT_GPIO_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-5	RESERVED	R	0h	Reserved
4-0	GPIO Event Enable	R/W	0h	GPIO Enable for PTP Event timestamping: Writing to these registers enables GPIOs for event timestamping by making them inputs Bit[0] = 1 : LED_0 is set as input Bit[1] = 1 : LED_1 is set as input Bit[2] = 1 : RX_ER is set as input Bit[3] = 1 : CLKOUT is set as input Bit[4] = 1 : GPIO_3 is set as input Bit[5] = 1 : GPIO_4 is set as input Bit[6] = 1 : GPIO_5 is set as input

8.2.142 TX_SMD_GPIO_CTL Register (Offset = D32h) [Reset = 001Fh]

TX_SMD_GPIO_CTL is shown in Table 8-146.

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This register controls the parsing of PTP frames with Dual VLAN Tag.

Table 8-146 TX_SMD_GPIO_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Dual VLAN Tag Parse Enable	R/W	0h	1b = Enable parsing of received packets with Dual VLAN tag
14	RESERVED	R	0h	Reserved
13-9	RESERVED	R	0h	Reserved
8-5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3-0	RESERVED	R	0h	Reserved

8.2.143 SCH_CTL_1 Register (Offset = D33h) [Reset = 0000h]

SCH_CTL_1 is shown in Table 8-147.

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Contains LSB 16-bits of step rate used by scheduler for scheduling large PPM adjustments.

Table 8-147 SCH_CTL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Scheduler Step Rate [15:0]	R/W	0h	Scheduler step rate for scheduling large PPM adjustment lower 16-bits: Bit 15:0 of 24-bit rate step used by scheduler (applicable only during permanent rate change and micro scheduler is used for rate change in small steps), resolution is 2^-32 ns. Calculate clock period from mr_base_freq[31:0] and then using desired step rate value in ppm, calculate step rate in ns. Scale the value by 2^-32 to obtain value to programmed to mr_step_rate.

8.2.144 SCH_CTL_2 Register (Offset = D34h) [Reset = 0300h]

SCH_CTL_2 is shown in Table 8-148.

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Contains MSB 8-bits of step rate used by scheduler for scheduling large PPM adjustments along with bypass options for PTP_PLL and accumulator.

Table 8-148 SCH_CTL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9	Bypass Scheduler for PTP PLL	R/W	1h	Bypass scheduler for PTP_PLL: Bypass scheduler controlled rate going to PTP_PLL (applicable only during permanent rate change). When this Bit is set and Bit 8 is not set, scheduler controlled rate adjustment is applied to the timer but PTP_PLL gets total PTP rate adjustment. When this bit as well as Bit 8 is set, scheduler based adjustment is bypassed.
8	Bypass Scheduler for Timer	R/W	1h	Bypass scheduler for Timer: Bypass scheduler controlled rate going to timer (applicable only during permanent rate change). When this Bit is set and Bit 9 is not set, scheduler controlled rate adjustment is applied to PTP_PLL but timer gets total PTP rate adjustment. When this bit as well as Bit 9 is set, scheduler based adjustment is bypassed.
7-0	Scheduler Step Rate [23:16]	R/W	0h	Scheduler step rate for scheduling large PPM adjustment MSB 8-bits: Bit 23:16 of 24-Bit rate step used by scheduler (applicable only during permanent rate change and when micro scheduler is used for rate change in small steps), resolution is 2^-32 ns. Calculate clock period from mr_base_freq[31:0]. Using desired step rate value in ppm, calculate step rate in ns. Scale the value by 2^-32 to obtain value to be programmed to mr_step_rate.

8.2.145 FREQ_CTL_1 Register (Offset = D35h) [Reset = CCCDh]

FREQ_CTL_1 is shown in Table 8-149.

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Contains LSB 16-bits of Base frequency programmable for PTP_PLL.

Table 8-149 FREQ_CTL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Base Frequency for PTP_PLL [15:0]	R/W	CCCDh	Base frequency programmable for PTP_PLL LSB word: Bit 15:0 of 32-bit programmable base frequency which is generated by PTP_PLL. 1 LSB represents 0.07275957614 Hz. Note Frequency value is modified only when 0xD35 and 0xD36 are written in sequence. This config decides the default clock frequency for PTP_PLL.

8.2.146 FREQ_CTL_2 Register (Offset = D36h) [Reset = CCCCh]

FREQ_CTL_2 is shown in Table 8-150.

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Contains MSB 16-bits of Base frequency programmable for PTP_PLL.

Table 8-150 FREQ_CTL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Base Frequency for PTP_PLL [31:16]	R/W	CCCCh	Base frequency programmable for PTP_PLL MSB word: Bit 31:16 of 32-bit programmable base frequency which is generated by PTP_PLL. 1 LSB represents 0.07275957614 Hz. Note: Frequency value is modified only when 0xD35 and 0xD36 are written in sequence. This config decides the default clock frequency for PTP_PLL.

8.2.147 PTP_RATEL_ACC_ONLY Register (Offset = D37h) [Reset = 0000h]

PTP_RATEL_ACC_ONLY is shown in Table 8-151.

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Contains LSB 16 bits of accumulator only rate adjustment value.

Table 8-151 PTP_RATEL_ACC_ONLY Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP Accumulator Rate Control [15:0]	R/W	0h	Rate Control value for PTP accumulator: Writing to this register sets the bits 15:0 of the Rate Control value for PTP accumulator when 0xD38[14] is set. The Rate Control value is in units of 2^-32 ns. This rate adjustment is not applied to PTP_PLL. PTP_PLL rate adjustment can still be controlled from registers 0xD04 and 0xD05.

8.2.148 PTP_RATEH_ACC_ONLY Register (Offset = D38h) [Reset = 0000h]

PTP_RATEH_ACC_ONLY is shown in Table 8-152.

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Contains MSB 10 bits of accumulator only rate adjustment value. Also contains enable and direction of accumulator only rate adjustment.

Table 8-152 PTP_RATEH_ACC_ONLY Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PTP Accumulator Direction	R/W	0h	PTP Rate ACC only Direction: The setting of this bit controls whether the device operates at a higher or lower frequency than the reference clock. This direction is applied along with 0xD37 and 0xD38[9:0] only if bit 0xD38[14] is set. 0 : Higher Frequency. The 'PTP Accumulator Rate Control' value is added to the clock on every cycle 1 : Lower Frequency. The 'PTP Accumulator Rate Control' value is subtracted from the clock on every cycle
14	PTP Accumulator Mode Enable	R/W	0h	PTP Accumulator mode: Setting this bit makes the PTP accumulator to be incremented according to registers 0xD37 and 0xD38[9:0] every clock cycle. 0h = accumulation value from 0xD04, 0xD05 1h = accumulation value from 0xD37, 0xD38[9:0]
13	PTP Accumulator Trate Enable	R/W	0h	PTP Temporary Rate Enable in Accumulator Mode: Setting this bit applies the temporary rate adjustments to the PTP Accumulator too (apart from the PTP PLL) 0h = Temporary Rate Adjustments are not applied to PTP Accumulator when Accumulator mode is enabled 1h = Temporary Rate Adjustments are applied to PTP Accumulator when Accumulator mode is enabled
12-10	RESERVED	R	0h	Reserved
9-0	PTP Accumulator Rate Control [25:16]	R/W	0h	PTP Rate ACC only high 10-bits: Writing to this register sets the bits 25:16 of the Rate Control value for PTP accumulator when 0xD38[14] is set. The Rate Control value is in units of 2^-32 ns. This rate adjustment does not applied to PTP_PLL. PTP_PLL rate adjustment is still controlled from registers 0xD04 and 0xD05.

8.2.149 PTP_PLL_CTL Register (Offset = D39h) [Reset = 0025h]

PTP_PLL_CTL is shown in Table 8-153.

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Table 8-153 PTP_PLL_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9	Half Rate Enable	R	0h	PTP_PLL set half rate: Set half rate for the NCO when in PLL_125M as ref clock mode.
8	PTP PLL Phase word [32]	R	0h	PTP_PLL phase word bit-32: Bit 32 of PTP_PLL phase word
7	Capture PTP Time	R/W	0h	Capture PTP time and PTP_PLL word: Used to capture the current 33-bit PTP_PLL word along with 64-bit PTP time. Setting this trigger stores PTP clock timestamp (32-bit seconds accumulator, 32-bit nanosecond accumulator ) and 33-bit PTP_PLL word simultaneously which can be read through 0xD39 - 0xD3F. This bit is self clearing.
6-0	PTP Scheduler Settle Timer	R/W	25h	PTP_PLL scheduler settle timer: No of cycles taken by PTP_PLL to provide jitter free output for any change in rate, defines the latency of rate change going to PTP_PLL. Used in scheduler every time the value of the PTP_PLL is changed.

8.2.150 PTP_PLL_RD_1 Register (Offset = D3Ah) [Reset = 0000h]

PTP_PLL_RD_1 is shown in Table 8-154.

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PTP timer nanosec counter readout value.

Table 8-154 PTP_PLL_RD_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP Timestamp [15:0]	R	0h	PTP time nano seconds LSB word: Bit 15 - 0 of PTP timer nano seconds counter.

8.2.151 PTP_PLL_RD_2 Register (Offset = D3Bh) [Reset = 0000h]

PTP_PLL_RD_2 is shown in Table 8-155.

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PTP timer nanosec counter readout value.

Table 8-155 PTP_PLL_RD_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP Timestamp [31:16]	R	0h	PTP time nano seconds MSB word: Bit 31 - 16 of PTP timer nano seconds counter.

8.2.152 PTP_PLL_RD_3 Register (Offset = D3Ch) [Reset = 0000h]

PTP_PLL_RD_3 is shown in Table 8-156.

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PTP timer seconds counter readout value.

Table 8-156 PTP_PLL_RD_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP Timestamp [47:32]	R	0h	PTP time seconds LSB word: Bit 15 - 0 of PTP timer seconds counter.

8.2.153 PTP_PLL_RD_4 Register (Offset = D3Dh) [Reset = 0000h]

PTP_PLL_RD_4 is shown in Table 8-157.

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PTP timer seconds counter readout value.

Table 8-157 PTP_PLL_RD_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP Timestamp [63:48]	R	0h	PTP time seconds MSB word: Bit 31 - 16 of PTP timer seconds counter.

8.2.154 PTP_PLL_RD_5 Register (Offset = D3Eh) [Reset = 0000h]

PTP_PLL_RD_5 is shown in Table 8-158.

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PTP_PLL phase word read out value.

Table 8-158 PTP_PLL_RD_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP Timestamp [79:64]	R	0h	PTP_PLL phase LSB word: Bit 15 - 0 of PTP_PLL phase word.

8.2.155 PTP_PLL_RD_6 Register (Offset = D3Fh) [Reset = 0000h]

PTP_PLL_RD_6 is shown in Table 8-159.

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PTP_PLL phase word read out value.

Table 8-159 PTP_PLL_RD_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PTP Timestamp [95:80]	R	0h	PTP_PLL phase MSB word: Bit 31 - 16 of PTP_PLL phase word.

8.2.156 PTP_ONESTEP_OFF Register (Offset = D40h) [Reset = 0000h]

PTP_ONESTEP_OFF is shown in Table 8-160.

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Controls offset value of onestep timestamp being inserted into the PTP packet.

Table 8-160 PTP_ONESTEP_OFF Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	PTP Accumulator Rate Control [31:26]	R/W	0h	PTP accumulator Rate Control value: Writing to this register sets bits 31:26 of the Rate Control value for PTP accumulator only when 0xD38[14] is set. The Rate Control value is in units of 2^-32 ns. This rate adjustment is not be applied to PTP_PLL. PTP_PLL rate adjustment is still controlled from registers 0xD04 and 0xD05.
9	PTP One-step Timestamp Offset Addition Enable	R/W	0h	PTP one-step timestamp offset addition enable: Setting this bit enables addition of the offset (loaded in 0xD40[8:0]) to the timestamp being inserted into the PTP packet during one-step timestamp insertion
8-0	PTP One-step Timestamp Offset	R/W	0h	PTP one-step timestamp offset: This offset value is added to the timestamp that is being inserted during one-step operation when 0xD40[9] is enabled.

8.2.157 PTP_PSF_VLAN_CFG_1 Register (Offset = D45h) [Reset = 0000h]

PTP_PSF_VLAN_CFG_1 is shown in Table 8-161.

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Configuration of VLAN tags for PSF packets

Table 8-161 PTP_PSF_VLAN_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	Dual VLAN Tag Enable for PSF	R/W	0h	1b = Enable addition of dual VLAN tag for PSF packets
0	VLAN Tag Enable for PSF	R/W	0h	1b = Enable addition of VLAN tag for PSF packet

8.2.158 PTP_PSF_VLAN_CFG_2 Register (Offset = D46h) [Reset = 0000h]

PTP_PSF_VLAN_CFG_2 is shown in Table 8-162.

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Configuration of VLAN tags for PSF packets

Table 8-162 PTP_PSF_VLAN_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	VLAN Tag 1 for PSF	R/W	0h	VLAN Tag 1 added to PSF packets when 0x0D45[0]=1

8.2.159 PTP_PSF_VLAN_CFG_3 Register (Offset = D47h) [Reset = 0000h]

PTP_PSF_VLAN_CFG_3 is shown in Table 8-163.

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Configuration of VLAN tags for PSF packets

Table 8-163 PTP_PSF_VLAN_CFG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	VLAN Tag 2 for PSF	R/W	0h	VLAN Tag 2 added to PSF packets when 0x0D45[1]=1

8.2.160 MAX_IPV4_LENGTH Register (Offset = D48h) [Reset = 0724h]

MAX_IPV4_LENGTH is shown in Table 8-164.

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Table 8-164 MAX_IPV4_LENGTH Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11-6	mr_ipv4_length_2	R/W	1Ch	Configure max packet length for PSF IPV4. Maximum value of IPv4 packet length is 0x3E
5-0	mr_ipv4_length_1	R/W	24h	Configure max packet length for PSF IPV4. Maximum value of IPv4 packet length is 0x3E

8.2.161 PTP_TXCFG_2 Register (Offset = D49h) [Reset = 0000h]

PTP_TXCFG_2 is shown in Table 8-165.

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Table 8-165 PTP_TXCFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-2	mr_ptp_domain_tx	R/W	0h	Sets ptp domain filtering for Tx packet
1	mr_pkt_cfg_en	R/W	0h	Sets whether configurability is enabled for DMAC/SMAC in PSF or not
0	tx_domain_en	R/W	0h	1b = Enable domain filtering on PTP TX 0b=Disable domain filtering on PTP TX

8.2.162 PSF_DMAC_1 Register (Offset = D4Ah) [Reset = 1B01h]

PSF_DMAC_1 is shown in Table 8-166.

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Table 8-166 PSF_DMAC_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_ipv4_dmac	R/W	1B01h	PSF DMAC byte_1 and byte_2 with bytes reversed (byte_2, byte_1)

8.2.163 PSF_DMAC_2 Register (Offset = D4Bh) [Reset = 0019h]

PSF_DMAC_2 is shown in Table 8-167.

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Table 8-167 PSF_DMAC_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_ipv4_dmac	R/W	19h	PSF DMAC byte_3 and byte_4 with bytes reversed (byte_4, byte_3)

8.2.164 PSF_DMAC_3 Register (Offset = D4Ch) [Reset = 0000h]

PSF_DMAC_3 is shown in Table 8-168.

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Table 8-168 PSF_DMAC_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_ipv4_dmac	R/W	0h	PSF DMAC byte_5 and byte_6 with bytes reversed (byte_6, byte_5)

8.2.165 PSF_SMAC_1 Register (Offset = D4Dh) [Reset = 0008h]

PSF_SMAC_1 is shown in Table 8-169.

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Table 8-169 PSF_SMAC_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_ipv4_smac	R/W	8h	PSF SMAC byte_1 and byte_2 with bytes reversed (byte_2, byte_1)

8.2.166 PSF_SMAC_2 Register (Offset = D4Eh) [Reset = 0B17h]

PSF_SMAC_2 is shown in Table 8-170.

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Table 8-170 PSF_SMAC_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_ipv4_smac	R/W	B17h	PSF SMAC byte_3 and byte_4 with bytes reversed (byte_4, byte_3)

8.2.167 PSF_SMAC_3 Register (Offset = D4Fh) [Reset = 0F6Bh]

PSF_SMAC_3 is shown in Table 8-171.

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Table 8-171 PSF_SMAC_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_ipv4_smac	R/W	F6Bh	PSF SMAC byte_5 and byte_6 with bytes reversed (byte_6, byte_5)

8.2.168 PSF_ETYPE Register (Offset = D50h) [Reset = F788h]

PSF_ETYPE is shown in Table 8-172.

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Table 8-172 PSF_ETYPE Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_ipv4_etype	R/W	F788h	PSF ether type byte_1, byte_2 for L2 packet with bytes reversed (byte_2, byte1)

8.2.169 IPV4_DA_1 Register (Offset = D51h) [Reset = 00E0h]

IPV4_DA_1 is shown in Table 8-173.

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Table 8-173 IPV4_DA_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_ipv4_da	R/W	E0h	PSF DA byte_1, byte_2 with bytes reversed (byte_2, byte_1)

8.2.170 IPV4_DA_2 Register (Offset = D52h) [Reset = 8101h]

IPV4_DA_2 is shown in Table 8-174.

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Table 8-174 IPV4_DA_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_ipv4_da	R/W	8101h	PSF DA byte_3, byte_4 with bytes reversed (byte_4, byte_3)

8.2.171 PSF_SOURCE_UDP_PORT Register (Offset = D53h) [Reset = 3F01h]

PSF_SOURCE_UDP_PORT is shown in Table 8-175.

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Table 8-175 PSF_SOURCE_UDP_PORT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_udp_s_port	R/W	3F01h	PSF S_PORT byte1, byte2 with byte reversed (byte_2, byte_1)

8.2.172 PSF_DESTINATION_UDP_PORT Register (Offset = D54h) [Reset = 3F01h]

PSF_DESTINATION_UDP_PORT is shown in Table 8-176.

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Table 8-176 PSF_DESTINATION_UDP_PORT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_pkt_sts_udp_d_port	R/W	3F01h	PSF D_PORT byte1, byte2 with byte reversed (byte_2, byte_1)

8.2.173 PTP_LAT_COMP_CTRL Register (Offset = DE0h) [Reset = C000h]

PTP_LAT_COMP_CTRL is shown in Table 8-177.

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Table 8-177 PTP_LAT_COMP_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	Dithering Latency Compensation Enable - Receive path	R/W	0h	Enable fixed latency compensation on the Rx side, when dithering is enabled, for 2-step PTP time stamping
2	Dithering Latency Compensation Enable - Transmit path	R/W	0h	Enable fixed latency compensation on the Tx side, when dithering is enabled, for 2-step PTP time stamping
1	Latency Compensation Enable - Receive path	R/W	0h	Enable fixed latency compensation on the Rx side, for 2-step PTP time stamping
0	Latency Compensation Enable - Transmit path	R/W	0h	Enable fixed latency compensation on the Tx side, for 2-step PTP time stamping

8.2.174 PTP_DEBUG_SEL Register (Offset = DF0h) [Reset = 0000h]

PTP_DEBUG_SEL is shown in Table 8-178.

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Table 8-178 PTP_DEBUG_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	PTP External Reference Support Enable	R/W	0h	In PTP external reference clock mode, by the default minimum frequency supported is >35 MHz. Set this bit to support lower frequencies (up to 25MHz)

8.2.175 MMD1_PMA_CTRL_1 Register (Offset = 1000h) [Reset = 0000h]

MMD1_PMA_CTRL_1 is shown in Table 8-179.

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Table 8-179 MMD1_PMA_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PMA Reset	R/W	0h	1b = PMA reset
14-1	RESERVED	R	0h	Reserved
0	PMA Loopback	R/W	0h	1b = PMA loopback set

8.2.176 MMD1_PMA_STATUS_1 Register (Offset = 1001h) [Reset = 0000h]

MMD1_PMA_STATUS_1 is shown in Table 8-180.

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Table 8-180 MMD1_PMA_STATUS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h	Reserved
2	Link Status	R	0h	1b = Link is up
1-0	RESERVED	R	0h	Reserved

8.2.177 MMD1_PMA_STAUS_2 Register (Offset = 1007h) [Reset = 003Dh]

MMD1_PMA_STAUS_2 is shown in Table 8-181.

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Table 8-181 MMD1_PMA_STAUS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5-0	PMA PMD Type Selection	R	3Dh	PMA or PMD type selection field 111101b = 100BASE-T1 PMA or PMD

8.2.178 MMD1_PMA_EXT_ABILITY_1 Register (Offset = 100Bh) [Reset = 0800h]

MMD1_PMA_EXT_ABILITY_1 is shown in Table 8-182.

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Table 8-182 MMD1_PMA_EXT_ABILITY_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	Extended Abilities	R	1h	1b = PMA/PMD has BASE-T1 extended abilities 0b = PMA/PMD does not have BASE-T1 extended abilities
10-0	RESERVED	R	0h	Reserved

8.2.179 MMD1_PMA_EXT_ABILITY_2 Register (Offset = 1012h) [Reset = 0001h]

MMD1_PMA_EXT_ABILITY_2 is shown in Table 8-183.

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Table 8-183 MMD1_PMA_EXT_ABILITY_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	0h	Reserved
0	100BASE-T1 Ability	R	1h	1b = PMA/PMD supports 100BASE-T1 0b = PMA/PMD does not support 100BASE-T1

8.2.180 MMD1_PMA_CTRL_2 Register (Offset = 1834h) [Reset = X000h]

MMD1_PMA_CTRL_2 is shown in Table 8-184.

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Table 8-184 MMD1_PMA_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	Leader Follower Configuration	R/W	0h	1b = Configure PHY as LEADER 0b = Configure PHY as FOLLOWER
13-4	RESERVED	R	0h	Reserved
3-0	type selection	R	0h	type selection field 0000b = 100Base-T1

8.2.181 MMD1_PMA_TEST_MODE_CTRL Register (Offset = 1836h) [Reset = 0000h]

MMD1_PMA_TEST_MODE_CTRL is shown in Table 8-185.

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Table 8-185 MMD1_PMA_TEST_MODE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	Compliance Test Mode	R/W	0h	100BASE-T1 test mode control 000b = Normal mode operation 001b = Test mode 1 010b = Test mode 2 011b = Reserved 100b = Test mode 4 101b = Test mode 5 110b = Reserved 111b = Reserved
12-0	RESERVED	R	0h	Reserved

8.2.182 MMD3_PCS_CTRL_1 Register (Offset = 3000h) [Reset = 0000h]

MMD3_PCS_CTRL_1 is shown in Table 8-186.

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Table 8-186 MMD3_PCS_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PCS Reset	R/W	0h	Reset bit, Self Clear. When write to this bit 1: 1. reset the registers (not vendor specific) at MMD3/MMD7. 2. Reset brk_top Please notice: This register is WSC (write-self-clear) and not read-only!
14	PCS Loopback	R/W	0h	This bit is cleared by PCS_Reset
13-11	RESERVED	R	0h	Reserved
10	RX Clock Stoppable	R/W	0h	RW, reset value = 1. 1= PHY can stop receive clock during LPI 0= Clock not stoppable Note: this flop implemented at glue logic
9-0	RESERVED	R	0h	Reserved

8.2.183 MMD3_PCS_Status_1 Register (Offset = 3001h) [Reset = 0000h]

MMD3_PCS_Status_1 is shown in Table 8-187.

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Table 8-187 MMD3_PCS_Status_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	TX LPI Received	RC	0h	1= Tx PCS hs received LPI 0= LPI not received
10	RX LPI Received	RC	0h	1= Rx PCS hs received LPI 0= LPI not received
9	TX LPI Indication	R	0h	1= TX PCS is currently receiving LPI 0= PCS is not currently receiving LPI
8	RX LPI Indication	R	0h	1= RX PCS is currently receiving LPI 0= PCS is not currently receiving LPI
7	RESERVED	R	0h	Reserved
6	TX Clock Stoppable	R	0h	1= the MAC can stop the clock during LPI 0= Clock not stoppable
5-0	RESERVED	R	0h	Reserved