SNLS779A July   2025  – November 2025 DP83TC815-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Power Domain
    2. 5.2 Pin States
    3. 5.3 Pin Multiplexing
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEEE802.1AS Features
        1. 7.3.1.1 PTP Clock Configuration
          1. 7.3.1.1.1 PTP Reference Clock
          2. 7.3.1.1.2 PTP Synchronized Clock (Wall Clock)
            1. 7.3.1.1.2.1 PTP Time Read or Write
            2. 7.3.1.1.2.2 PTP Clock Initialization
            3. 7.3.1.1.2.3 PTP Clock Adjustment
            4. 7.3.1.1.2.4 PTP Clock Output
              1. 7.3.1.1.2.4.1 One Pulse Per Second (PPS) Output
          3. 7.3.1.1.3 PTP Time Registers
        2. 7.3.1.2 Packet Timestamps
          1. 7.3.1.2.1 Transmit (Egress) Packet Parser and Timestamp
          2. 7.3.1.2.2 Receive (ingress) Packet Parser and Timestamp
          3. 7.3.1.2.3 PTP Transmit and Receive Timestamp Registers
        3. 7.3.1.3 Event Triggering and Timestamping
          1. 7.3.1.3.1 Event Triggering (Output)
            1. 7.3.1.3.1.1 Trigger Initialization
          2. 7.3.1.3.2 Event Timestamp (Input)
            1. 7.3.1.3.2.1 Timestamp Storage and Reading
          3. 7.3.1.3.3 Event Capture and Output Trigger Registers
        4. 7.3.1.4 PTP Interrupts
        5. 7.3.1.5 PTP I/O Configuration
      2. 7.3.2 TC10 Sleep Wake-up
        1. 7.3.2.1 Functions of the PHY for TC10 Support
          1. 7.3.2.1.1 Transition from Sleep to Wake-up Mode
            1. 7.3.2.1.1.1 Local Wake Detection
            2. 7.3.2.1.1.2 WUP Transmission and Reception
          2. 7.3.2.1.2 Wake Forwarding
          3. 7.3.2.1.3 Transition to Sleep - Sleep Negotiation
            1. 7.3.2.1.3.1 Sleep Ack
            2. 7.3.2.1.3.2 Sleep Request
            3. 7.3.2.1.3.3 Sleep Silent
            4. 7.3.2.1.3.4 Sleep Fail
            5. 7.3.2.1.3.5 Sleep
            6. 7.3.2.1.3.6 Force Sleep
        2. 7.3.2.2 Power Supply Networks for Sleep Applications
        3. 7.3.2.3 Configuration for Non-TC10 Applications
        4. 7.3.2.4 Miscellaneous Sleep Features
        5. 7.3.2.5 Fast Wake-up
      3. 7.3.3 PPM Monitor
      4. 7.3.4 Clock Dithering
      5. 7.3.5 Output Slew Control
      6. 7.3.6 Diagnostic Tool Kit
        1. 7.3.6.1 Signal Quality Indicator
        2. 7.3.6.2 Electrostatic Discharge Sensing
        3. 7.3.6.3 Time Domain Reflectometry
        4. 7.3.6.4 Voltage Sensing
        5. 7.3.6.5 Temperature Sensing
      7. 7.3.7 BIST and Loopback Modes
        1. 7.3.7.1 Data Generator and Checker
        2. 7.3.7.2 xMII Loopback
        3. 7.3.7.3 PCS Loopback
        4. 7.3.7.4 Digital Loopback
        5. 7.3.7.5 Analog Loopback
        6. 7.3.7.6 Reverse Loopback
      8. 7.3.8 Compliance Test Modes
        1. 7.3.8.1 Test Mode 1
        2. 7.3.8.2 Test Mode 2
        3. 7.3.8.3 Test Mode 4
        4. 7.3.8.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
        1. 7.4.1.1 Power Down
        2. 7.4.1.2 Reset
        3. 7.4.1.3 Standby
        4. 7.4.1.4 Normal
        5. 7.4.1.5 Sleep
      2. 7.4.2 Media Dependent Interface
        1. 7.4.2.1 100BASE-T1 Leader and 100BASE-T1 Follower Configuration
        2. 7.4.2.2 Auto-Polarity Detection and Correction
        3. 7.4.2.3 Jabber Detection
        4. 7.4.2.4 Interleave Detection
      3. 7.4.3 MAC Interfaces
        1. 7.4.3.1 Media Independent Interface
        2. 7.4.3.2 Reduced Media Independent Interface
        3. 7.4.3.3 Reduced Gigabit Media Independent Interface
        4. 7.4.3.4 Serial Gigabit Media Independent Interface
      4. 7.4.4 Serial Management Interface
        1. 7.4.4.1 Extended Register Space Access
        2. 7.4.4.2 Write Operation (No Post Increment)
        3. 7.4.4.3 Read Operation (No Post Increment)
        4. 7.4.4.4 Write Operation (Post Increment)
        5. 7.4.4.5 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
        1. 7.5.1.1 LED Configuration
  9. 8 Register Maps
    1. 8.1 Register Access Summary
    2. 8.2 DP83TC815 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Metal Pour
        4. 9.4.1.4 PCB Layer Stacking
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
100BASE-T1 PMA CONFORMANCE
VOD-MDI Output Differential Voltage RL(diff) = 100Ω 2.2 V
RMDI-Diff Integrated Differential Output Termination TRD_P and TRD_M 100 Ω
BOOTSTRAP DC CHARACTERISTICS (2 Level)
VMODE1 Mode 1 Strap Voltage Range  VDDIO = 3.3V ±7.5%, 2-level strap 0 0.8 V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 3.3V ±7.5%, 2-level strap 2 VDDIO V
VMODE1 Mode 1 Strap Voltage Range  VDDIO = 2.5V ±7.5%, 2-level strap 0 0.7 V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 2.5V ±7.5%, 2-level strap 1.7 VDDIO V
VMODE1 Mode 1 Strap Voltage Range  VDDIO = 1.8V ±7.5%, 2-level strap 0 0.35 x VDDIO V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 1.8V ±7.5%, 2-level strap 0.65 x VDDIO VDDIO V
BOOTSTRAP DC CHARACTERISTICS (3 Level)
VMODE1 Mode 1 Strap Voltage Range VDDIO = 3.3V ±7.5%, 3-level strap 0 0.18 x VDDIO V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 3.3V ±7.5%, 3-level strap 0.22 x VDDIO 0.42 x VDDIO V
VMODE3 Mode 3 Strap Voltage Range VDDIO = 3.3V ±7.5%, 3-level strap 0.46 x VDDIO  VDDIO V
VMODE1 Mode 1 Strap Voltage Range VDDIO = 2.5V ±7.5%, 3-level strap 0 0.25 x VDDIO V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 2.5V ±7.5%, 3-level strap 0.29 x VDDIO 0.56 x VDDIO V
VMODE3 Mode 3 Strap Voltage Range VDDIO = 2.5V ±7.5%, 3-level strap 0.65 x VDDIO  VDDIO V
VMODE1 Mode 1 Strap Voltage Range VDDIO = 1.8V ±7.5%, 3-level strap 0 0.35 x VDDIO V
VMODE2 Mode 2 Strap Voltage Range VDDIO = 1.8V ±7.5%, 3-level strap 0.40 x VDDIO 0.75 x VDDIO V
VMODE3 Mode 3 Strap Voltage Range VDDIO = 1.8V ±7.5%, 3-level strap 0.84 x VDDIO  VDDIO V
IO CHARACTERISTICS
VIH High Level Input Voltage VDDIO = 3.3V ±7.5% 2 V
VIL Low Level Input Voltage VDDIO = 3.3V ±7.5% 0.8 V
VOH High Level Output Voltage IOH = -2mA, VDDIO = 3.3V ±7.5% 2.4 V
VOL Low Level Output Voltage IOH = -2mA, VDDIO = 3.3V ±7.5% 0.4 V
VIH High Level Input Voltage VDDIO = 2.5V ±7.5% 1.7 V
VIL Low Level Input Voltage VDDIO = 2.5V ±7.5% 0.7 V
VOH High Level Output Voltage IOH = -2mA, VDDIO = 2.5V ±7.5% 2 V
VOL Low Level Output Voltage IOH = -2mA, VDDIO = 2.5V ±7.5% 0.4 V
VIH High Level Input Voltage VDDIO = 1.8V ±7.5% 0.65*VDDIO V
VIL Low Level Input Voltage VDDIO = 1.8V ±7.5% 0.35*VDDIO V
VOH High Level Output Voltage IOH = -2mA, VDDIO = 1.8V ±7.5% VDDIO-0.45 V
VOL Low Level Output Voltage IOH = -2mA, VDDIO = 1.8V ±7.5% 0.45 V
IIH Input High Current(1) VIN = VDDIO, All pins except XI and WAKE -10 10 µA
IIH-XI Input High Current(1) VIN = VDDIO, XI pin -15 15 µA
IIL-XI Input Low Current(1) VIN = GND, XI pin -15 15 µA
IIL Input Low Current(1) VIN = GND, All pins except XI, RESET_N pins -10 10 µA
IIL-RST Input Low Current VIN = GND, RESET pin -500 0 µA
Iozh Tri-state Output High Current(2) VIN = VDDIO, All pins except RX_CTRL and RX_ER -10 10 µA
Iozh Tri-state Output High Current(2) VIN = VDDIO, RX_CTRL and RX_ER -52 52 µA
Iozl Tri-state Output Low Current(2) VOUT = GND -10 10 µA
Rpulldn Internal Pull Down Resistor RX_D[3:0], RX_CLK, LED_0, LED_1, TX_CTRL 6.2 8.4 10.7 kΩ
Rpulldn Internal Pull Down Resistor RX_CTRL, RX_ER 4.725 5.8 7.2 kΩ
Rpulldn Internal Pull Down Resistor WAKE 320 455 590 kΩ
Rpullup Internal Pull Up Resistor INT, RESET 6.3 9 11.2 kΩ
XI VIH High Level Input Voltage 1.3 VDDIO V
XI VIL Low Level Input Voltage 0.5 V
CIN Input Capacitance XI 1 pF
CIN Input Capacitance INPUT PINS 5 pF
COUT Output Capacitance XO 1 pF
COUT Output Capacitance OUTPUT PINS 5 pF
Rseries Integrated MAC Series Termination Resistor RX_D[3:0], RX_ER, RX_DV, RX_CLK 35 50 65 Ω
Power Consumption VDDIO
I(VDDIO=3.3V) MII 20 25 mA
RMII 19 25 mA
RGMII 17 23 mA
SGMII 10 14 mA
I(VDDIO=2.5V) MII 14 18 mA
RMII 13 18 mA
RGMII 12 16 mA
SGMII 6 9 mA
I(VDDIO=1.8V) MII 10 13 mA
RMII 9 13 mA
RGMII 8 12 mA
SGMII 4 6 mA
I(VDDIO=3.3V) MII 802.1AS enabled 22 28 mA
RMII 23 28 mA
RGMII 20 28 mA
SGMII 13 22 mA
I(VDDIO=2.5V) MII 16 22 mA
RMII 15 21 mA
RGMII 14 19 mA
SGMII 8 15 mA
I(VDDIO=1.8V) MII 11 17 mA
RMII 11 17 mA
RGMII 8 17 mA
SGMII 6 12 mA
Power Consumption : Core Supplies
Single Supply: I(3V3) xMII 71 172 mA
SGMII 91 193 mA
Dual External Supply: I(3V3) xMII 48 70 mA
SGMII 68 91 mA
Dual External Supply: I(1V0) xMII 23 102 mA
SGMII 23 102 mA
Power Consumption : Core Supplies, 802.1AS enabled
Single Supply: I(3V3) xMII Sync Interval = 125ms 87 194 mA
SGMII 107 215 mA
Dual External Supply: I(3V3) xMII 60 83 mA
Dual External Supply: I(1V0) xMII 27 111 mA
Dual External Supply: I(3V3) SGMII 80 104 mA
Dual External Supply: I(1V0) SGMII 27 111 mA
Power Consumption: Low Power Modes
I(VDDA3V3) RESET Single supply 17 103 mA
I(VDDA3V3) Dual supply 9 21 mA
I(DVDD1P0) Dual supply 8 82 mA
I(VDDIO=3.3V) VDDIO = VDDMAC 12 18 mA
I(VDDIO=2.5V) 8.5 14 mA
I(VDDIO=1.8V) 6 10 mA
I(VDDA3V3) IEEE Power Down Single supply 15 98 mA
I(VDDA3V3) Dual supply 10 21 mA
I(VDDD1P0) Dual supply 5 77 mA
I(VDDIO=3.3V) VDDIO = VDDMAC 12 18 mA
I(VDDIO=1.8V) 8 11 mA
I(VDDIO=2.5V) 8 14 mA
I(VDDA3V3) Standby Single supply 31 119 mA
I(VDDA3V3) Dual supply 22 37 mA
I(DVDD1P0) Dual supply 9 82 mA
I(VDDIO=3.3V) xMII, VDDIO = VDDMAC 15 22 mA
SGMII, VDDIO = VDDMAC 12 15 mA
I(VDDIO=2.5V) xMII, VDDIO = VDDMAC 11 16 mA
SGMII, VDDIO = VDDMAC 8 13 mA
I(VDDIO=1.8V) xMII, VDDIO = VDDMAC 8 13 mA
SGMII, VDDIO = VDDMAC 6 8 mA
I(VSLEEP) TC-10 Sleep All other supplies are off 7 18 µA
All other supplies are off, Fast Wake-up mode enabled 25 50 µA
I(VDDIO=3.3V) TC-10 Sleep, supplies on VDDIO = VDDMAC 12 16 mA
I(VDDIO=2.5V) 8.5 12 mA
I(VDDIO=1.8V) 6 9 mA
I(VDDA3V3) Single supply 35 132 mA
I(VDDA3V3) Dual Supply 28 50 mA
I(VDDD1P0) Dual Supply 7 82 mA
SGMII Input
VIDTH Input differential voltage tolerance SI_P and SI_N, AC coupled 0.1 V
RIN-DIFF Receiver differential input impedance (DC) 80 120 ohm
SGMII Output
Clock signal duty cycle SO_P and SO_N, AC coupled, 0101010101 pattern 48 52 %
Output Differential Voltage SO_P and SO_N, AC coupled 150 400 mV
Voltage Sensor
VDDA VDDA  Sensor Range 2.7 3.3 4 V
VDDA Sensor Resolution (LSB) 8.8 mV
VDDA Sensor Accuracy Voltage and temperature variation on single part -150 150 mV
VDDA Sensor Accuracy Part-part variation -100 100 mV
VDDIO / VDDMAC VDDIO / VDDMAC  Sensor Range 1.44 3.9 V
VDDIO / VDDMAC Sensor Resolution (LSB) 16 mV
VDDIO / VDDMAC Sensor Accuracy Voltage and temperature variation on single part -200 200 mV
VDDIO / VDDMAC Sensor Accuracy Part-part variation -100 100 mV
VSLEEP VSLEEP Sensor Range Part-part and VT variation 2.7 3.3 4 V
VSLEEP Sensor Resolution (LSB) 8.8 mV
VSLEEP Sensor Accuracy Voltage and temperature variation on single part -150 150 mV
VSLEEP Sensor Accuracy Part-part variation -100 100 mV
VDD1P0 VDD1P0 Sensor Range 0.9 1 1.2 V
VDD1P0 Sensor Resolution (LSB) 2.7 mV
VDD1P0 Sensor Accuracy With room temp offset callibration on each part -60 60 mV
VDD1P0 Sensor Accuracy Part-to-part -40 40 mV
Temperature Sensor
Temp Temp Sensor Range -40 150 ℃
Temp Temp Sensor Resolution (LSB) 1.1 ℃
(1) For pins: MDC, TX_CLK, TX_CTRL, TX_D[3:0], and RESET_N
(2) For pins: RX_D[3:0], RX_CLK, RX_CTRL, MDIO, INT_N, and XO.