SNLS779A July   2025  – November 2025 DP83TC815-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Power Domain
    2. 5.2 Pin States
    3. 5.3 Pin Multiplexing
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEEE802.1AS Features
        1. 7.3.1.1 PTP Clock Configuration
          1. 7.3.1.1.1 PTP Reference Clock
          2. 7.3.1.1.2 PTP Synchronized Clock (Wall Clock)
            1. 7.3.1.1.2.1 PTP Time Read or Write
            2. 7.3.1.1.2.2 PTP Clock Initialization
            3. 7.3.1.1.2.3 PTP Clock Adjustment
            4. 7.3.1.1.2.4 PTP Clock Output
              1. 7.3.1.1.2.4.1 One Pulse Per Second (PPS) Output
          3. 7.3.1.1.3 PTP Time Registers
        2. 7.3.1.2 Packet Timestamps
          1. 7.3.1.2.1 Transmit (Egress) Packet Parser and Timestamp
          2. 7.3.1.2.2 Receive (ingress) Packet Parser and Timestamp
          3. 7.3.1.2.3 PTP Transmit and Receive Timestamp Registers
        3. 7.3.1.3 Event Triggering and Timestamping
          1. 7.3.1.3.1 Event Triggering (Output)
            1. 7.3.1.3.1.1 Trigger Initialization
          2. 7.3.1.3.2 Event Timestamp (Input)
            1. 7.3.1.3.2.1 Timestamp Storage and Reading
          3. 7.3.1.3.3 Event Capture and Output Trigger Registers
        4. 7.3.1.4 PTP Interrupts
        5. 7.3.1.5 PTP I/O Configuration
      2. 7.3.2 TC10 Sleep Wake-up
        1. 7.3.2.1 Functions of the PHY for TC10 Support
          1. 7.3.2.1.1 Transition from Sleep to Wake-up Mode
            1. 7.3.2.1.1.1 Local Wake Detection
            2. 7.3.2.1.1.2 WUP Transmission and Reception
          2. 7.3.2.1.2 Wake Forwarding
          3. 7.3.2.1.3 Transition to Sleep - Sleep Negotiation
            1. 7.3.2.1.3.1 Sleep Ack
            2. 7.3.2.1.3.2 Sleep Request
            3. 7.3.2.1.3.3 Sleep Silent
            4. 7.3.2.1.3.4 Sleep Fail
            5. 7.3.2.1.3.5 Sleep
            6. 7.3.2.1.3.6 Force Sleep
        2. 7.3.2.2 Power Supply Networks for Sleep Applications
        3. 7.3.2.3 Configuration for Non-TC10 Applications
        4. 7.3.2.4 Miscellaneous Sleep Features
        5. 7.3.2.5 Fast Wake-up
      3. 7.3.3 PPM Monitor
      4. 7.3.4 Clock Dithering
      5. 7.3.5 Output Slew Control
      6. 7.3.6 Diagnostic Tool Kit
        1. 7.3.6.1 Signal Quality Indicator
        2. 7.3.6.2 Electrostatic Discharge Sensing
        3. 7.3.6.3 Time Domain Reflectometry
        4. 7.3.6.4 Voltage Sensing
        5. 7.3.6.5 Temperature Sensing
      7. 7.3.7 BIST and Loopback Modes
        1. 7.3.7.1 Data Generator and Checker
        2. 7.3.7.2 xMII Loopback
        3. 7.3.7.3 PCS Loopback
        4. 7.3.7.4 Digital Loopback
        5. 7.3.7.5 Analog Loopback
        6. 7.3.7.6 Reverse Loopback
      8. 7.3.8 Compliance Test Modes
        1. 7.3.8.1 Test Mode 1
        2. 7.3.8.2 Test Mode 2
        3. 7.3.8.3 Test Mode 4
        4. 7.3.8.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
        1. 7.4.1.1 Power Down
        2. 7.4.1.2 Reset
        3. 7.4.1.3 Standby
        4. 7.4.1.4 Normal
        5. 7.4.1.5 Sleep
      2. 7.4.2 Media Dependent Interface
        1. 7.4.2.1 100BASE-T1 Leader and 100BASE-T1 Follower Configuration
        2. 7.4.2.2 Auto-Polarity Detection and Correction
        3. 7.4.2.3 Jabber Detection
        4. 7.4.2.4 Interleave Detection
      3. 7.4.3 MAC Interfaces
        1. 7.4.3.1 Media Independent Interface
        2. 7.4.3.2 Reduced Media Independent Interface
        3. 7.4.3.3 Reduced Gigabit Media Independent Interface
        4. 7.4.3.4 Serial Gigabit Media Independent Interface
      4. 7.4.4 Serial Management Interface
        1. 7.4.4.1 Extended Register Space Access
        2. 7.4.4.2 Write Operation (No Post Increment)
        3. 7.4.4.3 Read Operation (No Post Increment)
        4. 7.4.4.4 Write Operation (Post Increment)
        5. 7.4.4.5 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
        1. 7.5.1.1 LED Configuration
  9. 8 Register Maps
    1. 8.1 Register Access Summary
    2. 8.2 DP83TC815 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Metal Pour
        4. 9.4.1.4 PCB Layer Stacking
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

DP83TC815-Q1 DP83TC815-Q1 RHA Package36-Pin VQFNTop View Figure 5-1 DP83TC815-Q1 RHA Package36-Pin VQFNTop View
Table 5-1 Pin Functions
PIN STATE(1) DESCRIPTION
NAME(2) NO.
MAC INTERFACE
RX_CLK 27 S, PD, O

Receive Clock: In MII and RGMII modes, the receive clock provides a 25MHz reference clock.

Unused in RMII and SGMII modes

RX_D0

 26 S, PD, O

Receive Data: Symbols received on the cable are decoded and transmitted out of these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A data nibble, RX_D[3:0], is transmitted in MII and RGMII modes. 2 bits; RX_D[1:0], are transmitted in RMII mode.

If the PHY is bootstrapped to RMII Leader mode, a 50MHz clock reference is automatically outputted on RX_D3. This clock must be fed to the MAC.

RX_M / RX_P: Differential SGMII Data Output. These pins transmit data from the PHY to the MAC.

RX_D1 25
RX_D2 / RX_P 24
RX_D3 / RX_M 23
RX_DV / CRS_DV / RX_CTRL 15 S, PD, O

Receive Data Valid: This pin indicates when valid data is presented on RX_D[3:0] for MII mode.

Carrier Sense Data Valid: This pin combines carrier sense and data valid into an asynchronous signal. When CRS_DV is asserted, data is presented on RX_D[1:0] in RMII mode.

RGMII Receive Control: Receive control combines receive data valid indication and receive error indication into a single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is presented on the falling edge of RX_CLK.

Unused in SGMII mode
RX_ER / GPIO_6 14 S, PD, O

Receive Error: In MII and RMII modes, this pin indicates a receive error symbol has been detected within a received packet. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is optional in MII or RMII because the PHY automatically corrupts data on a receive error.

Unused in RGMII and SGMII modes

This pin can be used as GPIO_6.
TX_CLK 28 PD, I, O

Transmit Clock: In MII mode, the transmit clock is a 25MHz output (50 ohm Driver). In RGMII mode, this clock is sourced from the MAC layer to the PHY. A 25MHz clock must be provided in RGMII mode to meet the RGMII timing requirements mentioned in Timing Requirements.

Unused in RMII and SGMII modes
TX_D0 / TX_M 33 PD, I

Transmit Data: In MII and RGMII modes, the transmit data nibble, TX_D[3:0], is received from the MAC prior to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] is received from the MAC prior to the rising edge of the reference clock. TX_D[3:2] are not used in RMII mode.

TX_M / TX_P: Differential SGMII Data Input. These pins receive data that is transmitted from the MAC to the PHY.
TX_D1 / TX_P 32
TX_D2 31
TX_D3 33
TX_EN / TX_CTRL 29 PD, I

Transmit Enable: In MII mode, transmit enable is presented prior to the rising edge of the transmit clock. TX_EN indicates the presence of valid data inputs on TX_D[3:0]. In RMII Leader mode, transmit enable is presented prior to the rising edge of RX_D3. TX_EN indicates the presence of valid data inputs on TX_D[1:0].

RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication into a single signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented prior to the falling edge of TX_CLK.

Unused in SGMII mode
SERIAL MANAGEMENT INTERFACE
MDC 1 I

Management Data Clock: Synchronous clock to the MDIO serial management input and output data. This clock can be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 20MHz. There is no minimum clock rate.
MDIO 36 OD, IO

Management Data Input/Output: Bidirectional management data signal that can be sourced by the management station or the PHY. This pin requires a pullup resistor. In systems with multiple PHYs using same MDIO-MDC bus, a single pull-up resistor must be used on MDIO line.

Recommended to use a resistor between 2.2kΩ and 9kΩ.

MDIO/MDC Access is required to pass Open Alliance Compliance. See Section 7.3.8.
CONTROL INTERFACE
INH 10

O, OD

INH: Active-HIGH output. This pin is Hi-Z when the PHY is in TC-10 SLEEP. This pin is HIGH for all other PHY states. External pull down resistor in the range of 2kΩ - 10kΩ must be used when implementing TC-10 circuit. If multiple devices are sharing INH pin, then a single pull down resistor must be used.
INT 2 PU, OD, IO

Interrupt: Active-LOW output, asserts LOW when an interrupt condition occurs. This pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set, register access is required to clear the interrupt event. This pin can be configured as an Active-HIGH output using register 0x0011.

Interrupt status from Reg 12-13 is recommended to be read only when INT_N is LOW. This pin can also operate as Power-Down control where asserting this pin low would put the PHY in power down mode and asserting high would put the PHY in normal mode. This feature can also be enabled through register 0x0011.
RESET 3 PU, I

Reset: Active-LOW input, which initializes or reinitializes the PHY. Asserting this pin LOW for at least 1μs forces a reset process to occur. All internal registers reinitialize to the default states as specified for each bit in the Register Maps section. All bootstrap pins are resampled upon deassertion of reset.
WAKE 8

PD, I/O

WAKE: Input/Output pin which is Active-HIGH input by default. As input, this pin wakes the PHY from TC-10 SLEEP. Asserting this pin HIGH at power-up brings the PHY out of SLEEP. External 10kΩ pull down resistor can be used when implementing TC-10 circuit to prevent accidental wake-up. This pin can be directly tied to VSLEEP or it can be pulled to VSLEEP through a resistor to wake the device.

This pin also supports wake forwarding feature where a WAKE pulse generated by the PHY is then used to wake up other PHYs in the same system.
CLOCK INTERFACE
XI 5 I

Reference Clock Input (RMII): Reference clock 25MHz crystal or oscillator in RMII Leader mode.

Reference Clock Input (Other MAC Interfaces): Reference clock 25MHz crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating. This pin can also accept clock input from other devices like Ethernet MAC or another Ethernet PHY in daisy-chain operations.

If using a crystal, connect a 100Ω resistor in series with the XI pin
XO 4 O

Reference Clock Output: XO pin is used for crystal only. This pin must be left floating when a CMOS-level oscillator is connected to XI.
LED/GPIO INTERFACE
CLKOUT / GPIO_2 16 IO

Clock Output: 25MHz reference clock. This pin can also be used as LED or GPIO via Strap/Register selection. Program register<0x045F>=0x000F and register<0x0453>=0x0003 to disable switching on clkout pin
GPIO_3(3) 18 PD, IO General Purpose IO pins
GPIO_4 19 S, PD, IO
GPIO_5 20 PD, IO
LED_0 / GPIO_0 35 S, PD, IO

LED_0: Link Status LED. This pin can also be used as LED or clock output through Register selection.
LED_1 / GPIO_1 6 S, PD, IO

LED_1: Link Status and BLINK for TX/RX Activity. This pin can also be used as LED or clock output via Strap/Register selection.
MEDIUM DEPENDENT INTERFACE
TRD_M 13 IO

Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1 operation, IEEE 802.3bw compliant.
TRD_P 12
POWER CONNECTIONS
GND GND GROUND

Ground: This must always be connected to power ground.
LDO_OUT 9 SUPPLY

1.0V LDO Out: 1.0V Internal LDO Regulator Output

1.0V is generated internally from 3.3V VDDA Core supply.

Connect to VDD1P0 (Pin 21) for Single Supply Mode.

Leave floating for Dual Supply Mode
VDD1P0 21 SUPPLY

VDD1P0 Supply: 1.0V

Connect to LDO_OUT (Pin 9) for Single Supply Mode.

Connect to external regulator for Dual Supply Mode.

In Dual Supply Mode, recommend using ferrite bead and 2.2µF and 0.1µF ceramic decoupling capacitors.
VDDA 11 SUPPLY

Core Supply: 3.3V

Recommend using 0.47µF and 0.01µF ceramic decoupling capacitors; optional ferrite bead can be used.
VDDIO 34 SUPPLY

IO Supply: 1.8V, 2.5V, or 3.3V

Recommend using ferrite bead, 0.47µF and 0.01µF ceramic decoupling capacitors.

VDDMAC 22 SUPPLY

Optional MAC Interface Supply: 1.8V, 2.5V, or 3.3V

Optional separate supply for MAC interface pins. This pin supplies power to the MAC interface pins and can be kept at a different voltage level as compared to other IO pins. Recommend using 0.47µF, and 0.01µF ceramic decoupling capacitors and ferrite bead. When separate VDDMAC is not required in the system then it must be connected to VDDIO. When connecting to VDDIO, 0.47µF on the VDDIO can be removed. 0.47µF must still be connected close to VDDMAC. In this case, one common ferrite bead can be used between VDDIO and VDDMAC.

VSLEEP 7 SUPPLY

VSLEEP Supply: 3.3V

Recommend using 0.1µF ceramic decoupling capacitors.
DO NOT CONNECT
DNC 17 –

DNC: Do not connect (leave floating)
(1) Pin Type:
I = Input
O = Output
IO = Input/Output
OD = Open Drain
PD = Internal pulldown
PU = Internal pullup
S = Bootstrap configuration pin (all configuration pins have weak internal pullups or pulldowns)
(2) When pins are unused, follow the recommended connection requirements provided in the table above. If pins do not have required termination, the pins can be left floating.
(3) Do not drive the GPIO_3 HIGH before power-up.