SNLS779A July   2025  – November 2025 DP83TC815-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Power Domain
    2. 5.2 Pin States
    3. 5.3 Pin Multiplexing
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEEE802.1AS Features
        1. 7.3.1.1 PTP Clock Configuration
          1. 7.3.1.1.1 PTP Reference Clock
          2. 7.3.1.1.2 PTP Synchronized Clock (Wall Clock)
            1. 7.3.1.1.2.1 PTP Time Read or Write
            2. 7.3.1.1.2.2 PTP Clock Initialization
            3. 7.3.1.1.2.3 PTP Clock Adjustment
            4. 7.3.1.1.2.4 PTP Clock Output
              1. 7.3.1.1.2.4.1 One Pulse Per Second (PPS) Output
          3. 7.3.1.1.3 PTP Time Registers
        2. 7.3.1.2 Packet Timestamps
          1. 7.3.1.2.1 Transmit (Egress) Packet Parser and Timestamp
          2. 7.3.1.2.2 Receive (ingress) Packet Parser and Timestamp
          3. 7.3.1.2.3 PTP Transmit and Receive Timestamp Registers
        3. 7.3.1.3 Event Triggering and Timestamping
          1. 7.3.1.3.1 Event Triggering (Output)
            1. 7.3.1.3.1.1 Trigger Initialization
          2. 7.3.1.3.2 Event Timestamp (Input)
            1. 7.3.1.3.2.1 Timestamp Storage and Reading
          3. 7.3.1.3.3 Event Capture and Output Trigger Registers
        4. 7.3.1.4 PTP Interrupts
        5. 7.3.1.5 PTP I/O Configuration
      2. 7.3.2 TC10 Sleep Wake-up
        1. 7.3.2.1 Functions of the PHY for TC10 Support
          1. 7.3.2.1.1 Transition from Sleep to Wake-up Mode
            1. 7.3.2.1.1.1 Local Wake Detection
            2. 7.3.2.1.1.2 WUP Transmission and Reception
          2. 7.3.2.1.2 Wake Forwarding
          3. 7.3.2.1.3 Transition to Sleep - Sleep Negotiation
            1. 7.3.2.1.3.1 Sleep Ack
            2. 7.3.2.1.3.2 Sleep Request
            3. 7.3.2.1.3.3 Sleep Silent
            4. 7.3.2.1.3.4 Sleep Fail
            5. 7.3.2.1.3.5 Sleep
            6. 7.3.2.1.3.6 Force Sleep
        2. 7.3.2.2 Power Supply Networks for Sleep Applications
        3. 7.3.2.3 Configuration for Non-TC10 Applications
        4. 7.3.2.4 Miscellaneous Sleep Features
        5. 7.3.2.5 Fast Wake-up
      3. 7.3.3 PPM Monitor
      4. 7.3.4 Clock Dithering
      5. 7.3.5 Output Slew Control
      6. 7.3.6 Diagnostic Tool Kit
        1. 7.3.6.1 Signal Quality Indicator
        2. 7.3.6.2 Electrostatic Discharge Sensing
        3. 7.3.6.3 Time Domain Reflectometry
        4. 7.3.6.4 Voltage Sensing
        5. 7.3.6.5 Temperature Sensing
      7. 7.3.7 BIST and Loopback Modes
        1. 7.3.7.1 Data Generator and Checker
        2. 7.3.7.2 xMII Loopback
        3. 7.3.7.3 PCS Loopback
        4. 7.3.7.4 Digital Loopback
        5. 7.3.7.5 Analog Loopback
        6. 7.3.7.6 Reverse Loopback
      8. 7.3.8 Compliance Test Modes
        1. 7.3.8.1 Test Mode 1
        2. 7.3.8.2 Test Mode 2
        3. 7.3.8.3 Test Mode 4
        4. 7.3.8.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
        1. 7.4.1.1 Power Down
        2. 7.4.1.2 Reset
        3. 7.4.1.3 Standby
        4. 7.4.1.4 Normal
        5. 7.4.1.5 Sleep
      2. 7.4.2 Media Dependent Interface
        1. 7.4.2.1 100BASE-T1 Leader and 100BASE-T1 Follower Configuration
        2. 7.4.2.2 Auto-Polarity Detection and Correction
        3. 7.4.2.3 Jabber Detection
        4. 7.4.2.4 Interleave Detection
      3. 7.4.3 MAC Interfaces
        1. 7.4.3.1 Media Independent Interface
        2. 7.4.3.2 Reduced Media Independent Interface
        3. 7.4.3.3 Reduced Gigabit Media Independent Interface
        4. 7.4.3.4 Serial Gigabit Media Independent Interface
      4. 7.4.4 Serial Management Interface
        1. 7.4.4.1 Extended Register Space Access
        2. 7.4.4.2 Write Operation (No Post Increment)
        3. 7.4.4.3 Read Operation (No Post Increment)
        4. 7.4.4.4 Write Operation (Post Increment)
        5. 7.4.4.5 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
        1. 7.5.1.1 LED Configuration
  9. 8 Register Maps
    1. 8.1 Register Access Summary
    2. 8.2 DP83TC815 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Metal Pour
        4. 9.4.1.4 PCB Layer Stacking
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.4 Clock Dithering

To reduce the emissions from clock and data switching, DP83TC815-Q1 supports clock dithering on internal system clocks and MAC interface clock, data pins. The frequency of clocks is modulated with time to spread out the signal energy and reduce emissions. Figure 7-9 shows the example of dithered clock frequency using triangular and sawtooth profile, with time.

DP83TC815-Q1 Clock Dithering Frequency Profiles Figure 7-9 Clock Dithering Frequency Profiles

Dithering can be enabled and disabled using register 0x05A8. Separate options are available for enabling dithering of internal core clocks and MAC interface.

Note: Note: MAC interface dithering is only available for MII, RMII and RGMII interfaces. SGMII MAC interface outputs cannot be dithered.

To tweak the EMC performance, the following dithering options are available on DP83TC815-Q1

  • Dithering Profile:
    • Triangular and Sawtooth profiles are available
  • Dithering Modulation Period: Cycle time across which average of Δ(f) is 0.
    • EMC performance has higher improvement with higher modulation period.
  • Dithering Maximum Frequency Offset (Δ(f)): Configure maximum ratio of frequency offset w.r.t average frequency of the clock
    • EMC performance has higher improvement with higher Δ(f)

The above options are available from programming using registers 0x05A1 and 0x05A8

Impact of Dithering MAC Interface:

Dithering of clocks results in shrinkage and elongation of clock period of MAC interface signals over the modulation period. This causes the Inter-Packet Gap between packets to shrink or elongate. The output clock period of MAC interface reference clock also shrinks or elongates. Table 7-11 shows the comparison of Inter-Packet Gap and RGMII MAC interface period.

Table 7-11 IPG and Clock Period Variation with Dithering
S.NO Δf/f DITHER MODULATION TIME 25MHz CYCLE SLIPs IPG VARIATION 25MHz CLOCK PERIOD VARIATION
Sawtooth/Triangular
1 1% 8.33 us ±1 ±0.5 byte ±0.4ns
2 2% 8.33 us ±2 ±1 byte ±0.8ns
3 2% 16.66 us ±4 ±2 byte ±0.8ns

When MAC interface dithering is enabled, the compliance of Ethernet MAC to IPG shrinkage and Clock period variation must be made sure.