SNLS779A July   2025  – November 2025 DP83TC815-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Power Domain
    2. 5.2 Pin States
    3. 5.3 Pin Multiplexing
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEEE802.1AS Features
        1. 7.3.1.1 PTP Clock Configuration
          1. 7.3.1.1.1 PTP Reference Clock
          2. 7.3.1.1.2 PTP Synchronized Clock (Wall Clock)
            1. 7.3.1.1.2.1 PTP Time Read or Write
            2. 7.3.1.1.2.2 PTP Clock Initialization
            3. 7.3.1.1.2.3 PTP Clock Adjustment
            4. 7.3.1.1.2.4 PTP Clock Output
              1. 7.3.1.1.2.4.1 One Pulse Per Second (PPS) Output
          3. 7.3.1.1.3 PTP Time Registers
        2. 7.3.1.2 Packet Timestamps
          1. 7.3.1.2.1 Transmit (Egress) Packet Parser and Timestamp
          2. 7.3.1.2.2 Receive (ingress) Packet Parser and Timestamp
          3. 7.3.1.2.3 PTP Transmit and Receive Timestamp Registers
        3. 7.3.1.3 Event Triggering and Timestamping
          1. 7.3.1.3.1 Event Triggering (Output)
            1. 7.3.1.3.1.1 Trigger Initialization
          2. 7.3.1.3.2 Event Timestamp (Input)
            1. 7.3.1.3.2.1 Timestamp Storage and Reading
          3. 7.3.1.3.3 Event Capture and Output Trigger Registers
        4. 7.3.1.4 PTP Interrupts
        5. 7.3.1.5 PTP I/O Configuration
      2. 7.3.2 TC10 Sleep Wake-up
        1. 7.3.2.1 Functions of the PHY for TC10 Support
          1. 7.3.2.1.1 Transition from Sleep to Wake-up Mode
            1. 7.3.2.1.1.1 Local Wake Detection
            2. 7.3.2.1.1.2 WUP Transmission and Reception
          2. 7.3.2.1.2 Wake Forwarding
          3. 7.3.2.1.3 Transition to Sleep - Sleep Negotiation
            1. 7.3.2.1.3.1 Sleep Ack
            2. 7.3.2.1.3.2 Sleep Request
            3. 7.3.2.1.3.3 Sleep Silent
            4. 7.3.2.1.3.4 Sleep Fail
            5. 7.3.2.1.3.5 Sleep
            6. 7.3.2.1.3.6 Force Sleep
        2. 7.3.2.2 Power Supply Networks for Sleep Applications
        3. 7.3.2.3 Configuration for Non-TC10 Applications
        4. 7.3.2.4 Miscellaneous Sleep Features
        5. 7.3.2.5 Fast Wake-up
      3. 7.3.3 PPM Monitor
      4. 7.3.4 Clock Dithering
      5. 7.3.5 Output Slew Control
      6. 7.3.6 Diagnostic Tool Kit
        1. 7.3.6.1 Signal Quality Indicator
        2. 7.3.6.2 Electrostatic Discharge Sensing
        3. 7.3.6.3 Time Domain Reflectometry
        4. 7.3.6.4 Voltage Sensing
        5. 7.3.6.5 Temperature Sensing
      7. 7.3.7 BIST and Loopback Modes
        1. 7.3.7.1 Data Generator and Checker
        2. 7.3.7.2 xMII Loopback
        3. 7.3.7.3 PCS Loopback
        4. 7.3.7.4 Digital Loopback
        5. 7.3.7.5 Analog Loopback
        6. 7.3.7.6 Reverse Loopback
      8. 7.3.8 Compliance Test Modes
        1. 7.3.8.1 Test Mode 1
        2. 7.3.8.2 Test Mode 2
        3. 7.3.8.3 Test Mode 4
        4. 7.3.8.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
        1. 7.4.1.1 Power Down
        2. 7.4.1.2 Reset
        3. 7.4.1.3 Standby
        4. 7.4.1.4 Normal
        5. 7.4.1.5 Sleep
      2. 7.4.2 Media Dependent Interface
        1. 7.4.2.1 100BASE-T1 Leader and 100BASE-T1 Follower Configuration
        2. 7.4.2.2 Auto-Polarity Detection and Correction
        3. 7.4.2.3 Jabber Detection
        4. 7.4.2.4 Interleave Detection
      3. 7.4.3 MAC Interfaces
        1. 7.4.3.1 Media Independent Interface
        2. 7.4.3.2 Reduced Media Independent Interface
        3. 7.4.3.3 Reduced Gigabit Media Independent Interface
        4. 7.4.3.4 Serial Gigabit Media Independent Interface
      4. 7.4.4 Serial Management Interface
        1. 7.4.4.1 Extended Register Space Access
        2. 7.4.4.2 Write Operation (No Post Increment)
        3. 7.4.4.3 Read Operation (No Post Increment)
        4. 7.4.4.4 Write Operation (Post Increment)
        5. 7.4.4.5 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
        1. 7.5.1.1 LED Configuration
  9. 8 Register Maps
    1. 8.1 Register Access Summary
    2. 8.2 DP83TC815 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Metal Pour
        4. 9.4.1.4 PCB Layer Stacking
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
MII TIMING
T1.1 TX_CLK High / Low Time 16 20 24 ns
T1.2 TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK 10 ns
T1.3 TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK 0 ns
T2.1 RX_CLK High / Low Time 16 20 24 ns
T2.2 RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising 10 30 ns
RMII LEADER TIMING
T3.1 RMII Leader Clock Period 20 ns
RMII Leader Clock Duty Cycle 35 65 %
T3.2 TX_D[1:0], TX_ER, TX_EN Setup to RMII Leader Clock 4 ns
T3.3 TX_D[1:0], TX_ER, TX_EN Hold from RMII Leader Clock 2 ns
T3.4 RX_D[1:0], RX_ER, CRS_DV Delay from RMII Leader Clock rising edge 4 10 14 ns
RMII FOLLOWER TIMING
T3.1 Input Reference Clock Period 20 ns
Reference Clock Duty Cycle 35 65 %
T3.2 TX_D[1:0], TX_ER, TX_EN Setup to XI Clock rising 4 ns
T3.3 TX_D[1:0], TX_ER, TX_EN Hold from XI Clock rising 2 ns
T3.4 RX_D[1:0], RX_ER, CRS_DV Delay from XI Clock rising 4 14 ns
RGMII INPUT TIMING
Tcyc Clock Cycle Duration TX_CLK 36 40 44 ns
Tsetup(align) TX_D[3:0], TX_CTRL Setup to TX_CLK (Align Mode) 1 2 ns
Thold(align) TX_D[3:0], TX_CTRL Hold from TX_CLK (Align Mode) 1 2 ns
RGMII OUTPUT TIMING
Tskew(align) RX_D[3:0], RX_CTRL Delay from RX_CLK (Align Mode Enabled) On PHY Pins -1.2 1.2 ns
Tsetup(shift) RX_D[3:0], RX_CTRL Delay from RX_CLK (Shift Mode
Enabled, default)		 On PHY Pins 2 ns
Tcyc Clock Cycle Duration RX_CLK 36 40 44 ns
Duty_G Duty Cycle RX_CLK 45 50 55 %
SMI TIMING
T4.1 MDC to MDIO (Output) Delay Time 25pF load capacitance 0 40 ns
T4.2 MDIO (Input) to MDC Setup Time 10 ns
T4.3 MDIO (Input) to MDC Hold Time 10 ns
MDC Frequency 2.5 20 MHz
POWER-UP TIMING
T5.1 Supply ramp time: AVDD, DVDD, VDDIO (1) 0.2 8 ms
T5.1 Supply ramp time: Vsleep (1) 0.4 8 ms
T5.2 Supply ramp delay offset: For all supplies 10 ms
T5.3 XTAL Startup / Settling: Powerup to XI good/stabilized 1.5 ms
T5.4 Oscillator stabilization time from power up 10 ms
Last Supply power up, stable Clock To Reset Release 10 ms
T5.5 Post power-up to SMI ready: Post Power-up wait time required before MDC preamble can be sent for register access 10 ms
T5.6 Power-up to Strap latch-in 10 ms
T5.7 CLKOUT Startup/Settling: Powerup to CLKOUT good/stabilized 10 ms
T5.8 Power-up to idle stream 10 ms
RESET TIMING (RESET_N)
T6.1 Reset Pulse Width: Miminum Reset pulse width to be able to reset 100 µs
T6.2 Reset to SMI ready: Post reset wait time required before MDC preamble can be sent for register access 1 ms
T6.3 Reset to Strap latch-in: Hardware configuration pins transition to output drivers 80 µs
T6.4 Reset to idle stream 1800 µs
WAKE REQUEST AND WAKE PULSE TIMING
T7.1 Local Wake-Up Pulse Duration 40 µs
T7.2 Local Wake-Up to INH Transition 40 µs
T7.3 Energy-detect-based Wake-Up Pulse Duration 0.7 ms
T7.4 Energy-detect-based Wake-Up to INH Transition 0.7 ms
T7.5 Energy-detect-based Wake-Up to WAKE forwarding pulse 1.4 ms
TRANSMIT LATENCY TIMING
MII Rising edge TX_CLK with assertion TX_EN to SSD symbol on MD 190 275 ns
MII Rising edge TX_CLK with assertion TX_EN to SSD symbol on MD with PTP enabled 170 275 ns
Follower RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI 350 473 ns
Leader RMII Rising edge clock with assertion TX_EN to SSD symbol on MDI 340 462 ns
RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI 340 493 ns
First symbol of SGMII to SSD symbol on MDI 375 505 ns
RECEIVE LATENCY TIMING
SSD symbol on MDI to MII Rising edge of RX_CLK with assertion of RX_DV 420 530 ns
SSD symbol on MDI to MII Rising edge of RX_CLK with assertion of RX_DV With PTP enabled 450 600 ns
SSD symbol on MDI to Follower RMII Rising edge of XI clock with assertion of CRS_DV 499 660 ns
SSD symbol on MDI to Leader RMII Rising edge of Leader clock with assertion of CRS_DV 499 720 ns
SSD symbol on MDI to Rising edge of RGMII RX_CLK with assertion of RX_CTRL 450 590 ns
SSD symbol on MDI to first symbol of SGMII 727 884 ns
25 MHz OSCILLATOR REQUIREMENTS
Frequency Tolerance -100 +100 ppm
Rise / Fall Time (10%-90%) 8 ns
Jitter Tolerance (RMS) 25 ps
XI Duty Cycle in external clock mode 40 60 %
50 MHz OSCILLATOR REQUIREMENTS
Frequency 50 MHz
Frequency Tolerance and Stability Over temperature and aging –100 100 ppm
Rise / Fall Time (10% - 90%) 4 ns
Duty Cycle 35 65 %
25 MHz CRYSTAL REQUIREMENTS
Frequency 25 MHz
Frequency Tolerance and Stability Over temperature and aging –100 100 ppm
Equivalent Series Resistance 100 Ω
OUTPUT CLOCK TIMING (25 MHz)
Frequency (PPM) -100 100 -
Duty Cycle 40 60 %
Rise Time 5000 ps
Fall Time 5000 ps
Jitter (Short Term) 1000 ps
Frequency 25 MHz
802.1AS Synchronised Clock
802.1AS Synchronized Clock Frequency 1 50 MHz
Duty Cycle 45 55 %
Jitter (rms)  100 ps
Jitter (period)  400 ps
Jitter (cycle to cycle)  300 ps
1pps Output Synchronization Accuracy (802.1AS Clock source: Internal PLL/NCO DDS) - with optimized settings Offset Variation
across Reset cycles		 -30 30 ns
Jitter for a single
reset cycle		 -15 15 ns
Synchronization Accuracy (802.1AS Clock source: recovered Clock @200MHz ) - with optimized settings Offset Variation
across Reset cycles		 -30 30 ns
Jitter for a single
reset cycle		 -1 1 ns
(1) For supplies with ramp rate longer than 8ms, a RESET pulse is required after the last supply becomes stable.