SNVSCU9A May   2025  – November 2025 TPS7H4012-SEP , TPS7H4013-SEP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Quality Conformance Inspection
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VIN and Power VIN Pins (VIN and PVIN)
      2. 9.3.2 Voltage Reference
      3. 9.3.3 Voltage Sensing and Setting VOUT
        1. 9.3.3.1 Minimum Output Voltage
        2. 9.3.3.2 Maximum Output Voltage
      4. 9.3.4 Enable
      5. 9.3.5 Power Good (PWRGD)
      6. 9.3.6 Adjustable Switching Frequency and Synchronization
        1. 9.3.6.1 Internal Clock Mode
        2. 9.3.6.2 External Clock Mode
      7. 9.3.7 Turn-On Behavior
        1. 9.3.7.1 Soft-Start (SS_TR)
        2. 9.3.7.2 Safe Start-Up Into Prebiased Outputs
        3. 9.3.7.3 Tracking and Sequencing
      8. 9.3.8 Protection Modes
        1. 9.3.8.1 Overcurrent Protection
          1. 9.3.8.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 9.3.8.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 9.3.8.1.3 COMP Shutdown
          4. 9.3.8.1.4 Low-Side Overcurrent Sinking Protection
        2. 9.3.8.2 Output Overvoltage Protection (OVP)
        3. 9.3.8.3 Thermal Shutdown
      9. 9.3.9 Error Amplifier and Loop Response
        1. 9.3.9.1 Error Amplifier
        2. 9.3.9.2 Power Stage Transconductance
        3. 9.3.9.3 Slope Compensation
        4. 9.3.9.4 Frequency Compensation
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Operating Frequency
        2. 10.2.2.2  Output Inductor Selection
        3. 10.2.2.3  Output Capacitor Selection
        4. 10.2.2.4  Input Capacitor Selection
        5. 10.2.2.5  Soft-Start Capacitor Selection
        6. 10.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 10.2.2.7  Output Voltage Feedback Resistor Selection
        8. 10.2.2.8  Output Voltage Accuracy
        9. 10.2.2.9  Slope Compensation Requirements
        10. 10.2.2.10 Compensation Component Selection
        11. 10.2.2.11 Schottky Diode
      3. 10.2.3 Application Curve
      4. 10.2.4 Inverting Buck-Boost
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1.     82

6 Pin Configuration and Functions

TPS7H4012-SEP TPS7H4013-SEP HLC Package, 20-Pin CFP (Top View)Figure 6-1 HLC Package, 20-Pin CFP
(Top View)
TPS7H4012-SEP TPS7H4013-SEP DDW Package, 44-Pin HTSSOP (Top View)Figure 6-2 DDW Package, 44-Pin HTSSOP
(Top View)
Table 6-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME CFP
(20)		 HTSSOP
(44)
GND 1 1, 2 — Ground. Return for control circuitry.
EN 2 3 I Enable. Driving this pin to logic high enables the device; driving the pin to logic low disables the device. A resistor divider from VIN to GND may be used to set the device turn-on level.
RT 3 4 I/O A resistor connected between RT and GND sets the switching frequency of the converter. The switching frequency range is 100kHz to 1MHz. If the device is configured to utilize an external clock, this pin may be left floating or a resistor may be used to provide a backup frequency if the external clock is lost.
VIN 4 5 I Input voltage. Power for the control circuitry of the switching regulator. It must be the same voltage as PVIN and is therefore recommended to externally connect VIN to PVIN.
LDOCAP 5 6 O Linear regulator output capacitor pin. A 1µF capacitor must be placed on this pin for the internal linear regulator. The output voltage, AVDD, is nominally 5V. Do not load this pin with any additional external circuitry.
SYNC1 6 8 I Synchronization pin 1. This pin is used as an input for an external clock. It will set the switching frequency 180° out of phase with SYNC1. If an external clock is not used, it is recommended to connect SYNC1 to GND to prevent noise coupling into the pin.
PVIN 7–8 11–15 I Power stage input voltage. Power for the output stage of the switching regulator.
PGND 9–10 16–22 — Power stage ground. Return for low-side power MOSFET. Connect to GND on the PCB.
SW 11–14 23–34 O Switching node pins. Switch node output. A Schottky diode may be connected from SW to PGND for potential improvement in internal device noise and efficiency.
PWRGD 15 36 O Power Good pin. This is an open-drain pin. Use a pull-up resistor to pull this pin up to VOUT (assuming VOUT is under 7V) or the desired logic level. PWRGD is asserted when the output voltage is within 5% (typ) of its programmed value. PWRGD is deasserted when the output voltages is outside 8% (typ) of its programmed value or when there is a fault condition (such as thermal shutdown).
RSC 16 39 I/O Slope compensation pin. A resistor from RSC to GND sets the desired slope compensation.
SS_TR 17 40 I/O Soft-start and tracking. An external capacitor connected between this pin and VSNS- slows down the rise time of the internal reference. It can also be used for tracking and sequencing.
VSNS+ 18 42 I Positive voltage sense. This is the feedback pin that will be set to a nominal 0.6V by selecting the appropriate resistor divider network.
COMP 19 43 I/O Compensation pin. This is the operational transconductance (OTA) error amplifier output and input to the switch current comparator. Connect frequency compensation to this pin.
REFCAP 20 44 O Reference capacitor pin. A 470nF external capacitor is required for the internal bandgap reference. The voltage, VBG, is nominally 1.2V. Do not connect external circuitry to this pin.
NC1 N/A 10, 35, 38,41 — No connect 1. These pins are not internally connected. It is recommended to connect these pins to GND to prevent charge buildup; however, these pins can also be left open or tied to any voltage between GND and VIN.
NC2 N/A 7, 9, 37 — No connect 2. These pins are internally connected. Do not externally connect these pins (they must be left electrically floating). They will internally be pulled to a voltage between GND and LDOCAP.
THERMAL PAD 21 45 — Thermal pad internally connected to GND. Connect to a large ground plane for thermal dissipation. While it is recommended to electrically connect to GND or PGND; it may be left electrically disconnected if desired.
Metal lid Lid N/A — Internally connected to GND.
(1) I = Input, O = Output, I/O = Input or Output, — = Other