SNVSCU9A May   2025  – November 2025 TPS7H4012-SEP , TPS7H4013-SEP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Quality Conformance Inspection
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VIN and Power VIN Pins (VIN and PVIN)
      2. 9.3.2 Voltage Reference
      3. 9.3.3 Voltage Sensing and Setting VOUT
        1. 9.3.3.1 Minimum Output Voltage
        2. 9.3.3.2 Maximum Output Voltage
      4. 9.3.4 Enable
      5. 9.3.5 Power Good (PWRGD)
      6. 9.3.6 Adjustable Switching Frequency and Synchronization
        1. 9.3.6.1 Internal Clock Mode
        2. 9.3.6.2 External Clock Mode
      7. 9.3.7 Turn-On Behavior
        1. 9.3.7.1 Soft-Start (SS_TR)
        2. 9.3.7.2 Safe Start-Up Into Prebiased Outputs
        3. 9.3.7.3 Tracking and Sequencing
      8. 9.3.8 Protection Modes
        1. 9.3.8.1 Overcurrent Protection
          1. 9.3.8.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 9.3.8.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 9.3.8.1.3 COMP Shutdown
          4. 9.3.8.1.4 Low-Side Overcurrent Sinking Protection
        2. 9.3.8.2 Output Overvoltage Protection (OVP)
        3. 9.3.8.3 Thermal Shutdown
      9. 9.3.9 Error Amplifier and Loop Response
        1. 9.3.9.1 Error Amplifier
        2. 9.3.9.2 Power Stage Transconductance
        3. 9.3.9.3 Slope Compensation
        4. 9.3.9.4 Frequency Compensation
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Operating Frequency
        2. 10.2.2.2  Output Inductor Selection
        3. 10.2.2.3  Output Capacitor Selection
        4. 10.2.2.4  Input Capacitor Selection
        5. 10.2.2.5  Soft-Start Capacitor Selection
        6. 10.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 10.2.2.7  Output Voltage Feedback Resistor Selection
        8. 10.2.2.8  Output Voltage Accuracy
        9. 10.2.2.9  Slope Compensation Requirements
        10. 10.2.2.10 Compensation Component Selection
        11. 10.2.2.11 Schottky Diode
      3. 10.2.3 Application Curve
      4. 10.2.4 Inverting Buck-Boost
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1.     82

5 Device Options Table

GENERIC PART NUMBER RADIATION RATING(1) GRADE(2) PACKAGE ORDERABLE PART NUMBER
TPS7H4012SP TID of 100krad(Si) RLAT, DSEE free to 75MeV-cm2/mg QMLV-RHA 20-pin CFP HLC 5962R2122105VZC(4)
QMLP-RHA(3) 44-pin HTSSOP DDW 5962R2122103PYE(4)
None Engineering model(3) 20-pin CFP HLC TPS7H4012HLC/EM(4)
TPS7H4012-SEP TID of 50krad(Si) RLAT, DSEE free to 43MeV-cm2/mg Space Enhanced Plastic 44-pin HTSSOP DDW TPS7H4012MDDWTSEP
TPS7H4013SP TID of 100krad(Si) RLAT, DSEE free to 75MeV-cm2/mg QMLV-RHA 20-pin CFP HLC 5962R2122106VZC(4)
QMLP-RHA(3) 44-pin HTSSOP DDW 5962R2122104PYE(4)
None Engineering model(3) 20-pin CFP HLC TPS7H4013HLC/EM(4)
TPS7H4013-SEP TID of 50krad(Si) RLAT, DSEE free to 43MeV-cm2/mg Space Enhanced Plastic 44-pin HTSSOP DDW TPS7H4013MDDWTSEP
SN0020HLC N/A Mechanical "dummy" package (no die) 20-pin CFP HLC SN0020HLC
(1) TID is total ionizing dose and DSEE is destructive single event effects. Additional information is available in the associated TID reports and SEE reports for each product.
(2) For additional information about the part grade, view part ratings.
(3) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (such as no burn-in and only 25°C testing). These units are not suitable for qualification, production, radiation testing, or flight use. Parts are not warranted as to performance over temperature or operating life.
(4) Product preview.