SNVSCU9A May   2025  – November 2025 TPS7H4012-SEP , TPS7H4013-SEP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Quality Conformance Inspection
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VIN and Power VIN Pins (VIN and PVIN)
      2. 9.3.2 Voltage Reference
      3. 9.3.3 Voltage Sensing and Setting VOUT
        1. 9.3.3.1 Minimum Output Voltage
        2. 9.3.3.2 Maximum Output Voltage
      4. 9.3.4 Enable
      5. 9.3.5 Power Good (PWRGD)
      6. 9.3.6 Adjustable Switching Frequency and Synchronization
        1. 9.3.6.1 Internal Clock Mode
        2. 9.3.6.2 External Clock Mode
      7. 9.3.7 Turn-On Behavior
        1. 9.3.7.1 Soft-Start (SS_TR)
        2. 9.3.7.2 Safe Start-Up Into Prebiased Outputs
        3. 9.3.7.3 Tracking and Sequencing
      8. 9.3.8 Protection Modes
        1. 9.3.8.1 Overcurrent Protection
          1. 9.3.8.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 9.3.8.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 9.3.8.1.3 COMP Shutdown
          4. 9.3.8.1.4 Low-Side Overcurrent Sinking Protection
        2. 9.3.8.2 Output Overvoltage Protection (OVP)
        3. 9.3.8.3 Thermal Shutdown
      9. 9.3.9 Error Amplifier and Loop Response
        1. 9.3.9.1 Error Amplifier
        2. 9.3.9.2 Power Stage Transconductance
        3. 9.3.9.3 Slope Compensation
        4. 9.3.9.4 Frequency Compensation
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Operating Frequency
        2. 10.2.2.2  Output Inductor Selection
        3. 10.2.2.3  Output Capacitor Selection
        4. 10.2.2.4  Input Capacitor Selection
        5. 10.2.2.5  Soft-Start Capacitor Selection
        6. 10.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 10.2.2.7  Output Voltage Feedback Resistor Selection
        8. 10.2.2.8  Output Voltage Accuracy
        9. 10.2.2.9  Slope Compensation Requirements
        10. 10.2.2.10 Compensation Component Selection
        11. 10.2.2.11 Schottky Diode
      3. 10.2.3 Application Curve
      4. 10.2.4 Inverting Buck-Boost
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1.     82

7.5 Electrical Characteristics

Over 4.5V ≤ VIN ≤ 14V, PVIN = VIN, open loop configuration, IOUT = 0A, over operating temperature range (TA = –55°C to 125°C), unless otherwise noted; includes RLAT at TA = 25°C if sub-group number is present for QML RHA and SEP devices(1)
PARAMETER TEST CONDITIONS SUB-GROUP(2) MIN TYP MAX UNIT
POWER SUPPLIES AND CURRENTS
VUVLOR_PVIN PVIN internal UVLO rising threshold 1, 2, 3 3.2 3.4 3.6 V
VUVLOHYST_PVIN PVIN internal UVLO hysteresis 1, 2, 3 425 450 500 mV
VUVLOR_VIN VIN internal UVLO rising threshold 1, 2, 3 3.4 3.6 3.8 V
VUVLOHYST_VIN VIN internal UVLO hysteresis 1, 2, 3 140 155 170 mV
ISHDN_VIN VIN shutdown supply current VEN = 0V VIN = 4.5V 1, 2, 3 2 2.9 mA
VIN = 14V 1, 2, 3 2 3
ISHDN_PVIN PVIN shutdown supply current VEN = 0V PVIN = 4.5V 1, 2, 3 2.6 3.5 mA
PVIN = 14V 1, 2, 3 3.5 4.7
IQ_VIN VIN operating quiescent current (non switching) VEN = 7V, VSNS+ = 1V 1, 2, 3 2.6 5 mA
ENABLE
VEN(rising) Enable rising threshold (turn-on) 1, 2, 3 0.555 0.61 0.655 V
VEN(falling) Enable falling threshold (turn-off) 1, 2, 3 0.455 0.51 0.554
tEN(delay) Enable propogation delay EN high to SW high, SS pin open 1, 2, 3 52 100 µs
IEN(LKG) Enable input leakage current VEN = 7V 1, 2, 3 2 100 nA
VOLTAGE REFERENCE AND SENSE
VREF Internal voltage reference (including error amplifier VIO) see (3) TA = –55℃ 3 0.594 0.598 0.603 V
TA = 25℃ 1 0.596 0.6 0.603
TA = 125℃ 2 0.597 0.6 0.604
VREF(internal) Internal voltage reference (without error amplifier included) VREF(internal) = VSS_TR 1, 2, 3 0.593 0.6 0.606 V
VBG Bandgap voltage (voltage at the REFCAP pin) CREFCAP = 470nF 1, 2, 3 1.184 1.2 1.222 V
IVSNS+(LKG) VSNS+ input leakage current  VSNS+ = 0.6V 1, 2, 3 10 30 nA
ERROR AMPLIFIER
VIO Error amplifier input offset voltage  VSNS+ = 0.6V 1, 2, 3 –2.9 2.9 mV
gmEA Error amplifier transconductance –10μA < ICOMP < 10μA, VCOMP = 1V TA = –55℃ 11 1400 2050 2700 µS
TA = 25℃ 9 1200 1650 2100
TA = 125℃ 10 1000 1250 1500
EADC Error amplifier DC gain  VSNS+ = 0.6V 11500 V/V
EAISRC Error amplifier source VCOMP = 1V, 100mV input overdrive 1, 2, 3 90 125 200 µA
EAISNK Error amplifier sink 90 125 200
EARo Error amplifier output resistance 7 MΩ
EABW Error amplifier bandwidth 9 MHz
gmps Power stage transconductance VCOMP = 0.7V TPS7H4012, HTSSOP 1, 2, 3 8 11.2 14.5 S
VCOMP = 0.7V TPS7H4012, CFP 11
VCOMP = 0.75V TPS7H4013, HTSSOP 1, 2, 3 3.5 6.2 9.2
VCOMP = 0.75V TPS7H4013, CFP 7.2
OVERCURRENT PROTECTION
IOC_HS1 High-side switch current limit
threshold 1(4)		 RSHORT = 100mΩ TPS7H4012, HTSSOP 1, 2, 3 9.7 12.2 A
TPS7H4012, CFP 9.5
TPS7H4013, HTSSOP 1, 2, 3 5.6 7.7
TPS7H4013, CFP 5.5
IOC_HS2 High-side switch current limit
threshold 2		 VIN = 12V,
RSHORT ≈ 4mΩ		 TPS7H4012, HTSSOP 1, 2, 3 11.8 A
TPS7H4012, CFP 11.5
TPS7H4013, HTSSOP 1, 2, 3 6.8
TPS7H4013, CFP 6.6
IOC_LS(sink) Low-side switch sinking overcurrent threshold TA = –55°C 3 2 A
TA = 25°C 1 1.9
TA = 125°C 2 1.7
COMPSHDN COMP shutdown voltage 1, 2, 3 1.7 1.9 2.1 V
tCOMP(delay) COMP shutdown delay 30 µs
SOFT START AND TRACKING
tSS Soft start time VSS_TR from 10% to 90%, 
VOUT(set) = 3.3V		 CSS = 5.6nF 9, 10, 11 1.5 ms
CSS = 22nF 9, 10, 11 4.7 5.8 7.3
CSS = 100nF 9, 10, 11 24.7
RSS(discharge) Soft start discharge pull-down resistor 1, 2, 3 200 442 700 Ω
SSstartup Maximum voltage on SS before startup(5) 20 mV
SLOPE COMPENSATION
SC Slope compensation, TPS74012 fSW = 100kHz,
VIN = 12V		 RSC = 499kΩ –0.8 A/µs
RSC = 1.5MΩ –0.3
fSW = 500kHz,
VIN = 12V		 RSC = 100kΩ –4.2
RSC = 499kΩ –1.4
RSC = 1.5MΩ –1
fSW = 1000kHz,
VIN = 12V		 RSC = 100kΩ –5.5
RSC = 499kΩ –2.4
RSC = 1.5MΩ –2.3
SC Slope compensation, TPS74013 fSW = 100kHz,
VIN = 12V		 RSC = 499kΩ –0.5 A/µs
RSC = 1.5MΩ –0.2
fSW = 500kHz,
VIN = 12V		 RSC = 100kΩ –2.8
RSC = 499kΩ –1.2
RSC = 1.5MΩ –0.8
fSW = 1000kHz,
VIN = 12V		 RSC = 100kΩ –4
RSC = 499kΩ –2
RSC = 1.5MΩ –1.5
MINIMUM ON TIME AND DEAD TIME
ton(min) Minimum on time 50% to 50% of VIN,
ISW = 2A		 VIN = 4.5V 9, 10, 11 210 235 ns
VIN = 5V 9, 10, 11 213 250
VIN = 12V 9, 10, 11 199 250
VIN = 14V 9, 10, 11 199 250
toff(min) Minimum off time ISW = 2A 306 ns
tdead Dead time 70 ns
SWITCHING FREQUENCY AND SYNCHRONIZATION
fSW RT programmed switching frequency RRT = 511kΩ 4, 5, 6 90 100 120 kHz
RRT = 90.9kΩ 4, 5, 6 450 500 550
RRT = 40.2kΩ VIN = 4.5V 4, 5, 6 850 1000 1150
5 ≤ VIN ≤ 14 4, 5, 6 870 1000 1170
tSYNC_D SYNC1 to SW delay SYNC1 input, see Figure 8-2

 VIN = 4.5V 9, 10, 11 150 256 390 ns
5V ≤ VIN ≤ 14V 9, 10, 11 160 240 310
VIN = 12V,
IOUT = 3A		 246
VSYNC1(IH) SYNC1 input high threshold 1, 2, 3 1.7 V
VSYNC1(IL) SYNC1 input low threshold 1, 2, 3 0.7
fSYNC SYNC1 input frequency range 4, 5, 6 100 1000 kHz
DSYNC SYNC1 input duty cycle range External clock duty cycle 4, 5, 6 40% 60%
tCLK_E_I External clock to internal clock detection time RT populated 9, 10, 11 2 5 (1/fsw) s
tCLK_I_E Internal clock to external clock detection time RT populated 9, 10, 11 1 2 (1/fsw) s
POWER GOOD AND THERMAL SHUTDOWN
PWRGDLOW_F% PWRGD falling threshold (fault), low Threshold for PWRGD (VSNS+ as percent of VREF) VSNS+ falling 1, 2, 3 89% 92% 95%
PWRGDLOW_R% PWRGD rising threshold (good), low VSNS+ rising 1, 2, 3 92% 95% 98%
PWRGDHIGH_R% PWRGD rising threshold (fault), high VSNS+ rising 1, 2, 3 105% 108% 112%
PWRGDHIGH_F% PWRGD falling threshold (good), high VSNS+ falling 1, 2, 3 102% 105% 109%
IPWRGD(LKG) Output high leakage VSNS+ = VREF, VPWRGD = 7V 1, 2, 3 50 500 nA
VPWRGD(OL) Power good output low IPWRGD(SINK) = 0mA to 2mA 1, 2, 3 250 300 mV
VINMIN_PWRGD Minimum VIN for valid PWRGD output Measured when VPWRGD ≤ 0.5V at 100μA 1, 2, 3 1 2 V
TSD(enter) Thermal shutdown enter temperature 175 °C
TSD(exit) Thermal shutdown exit temperature 140
TSD(HYS) Thermal shutdown hysteresis 35
MOSFET
RDS_ON_HS High-side switch resistance at
IHS = 6A, TPS7H4012, HTSSOP		 PVIN = 4.5V TA = –55℃ 3 29 42 mΩ
TA = 25℃ 1 37 48
TA = 125℃ 2 47 63
5V ≤ PVIN ≤ 14V TA = –55℃ 3 26 38
TA = 25℃ 1 33 46
TA = 125℃ 2 41 56
RDS_ON_LS Low-side switch resistance at
ILS = 6A, TPS7H4012, HTSSOP		 PVIN = 4.5V TA = –55℃ 3 20 31 mΩ
TA = 25℃ 1 28 39
TA = 125℃ 2 41 50
5V ≤ PVIN ≤ 14V TA = –55℃ 3 20 29
TA = 25℃ 1 27 37
TA = 125℃ 2 39 48
RDS_ON_HS High-side switch resistance at
IHS = 6A, TPS7H4012, CFP(6)		 PVIN = 4.5V TA = –55℃ 3 43 58 mΩ
TA = 25℃ 1 55 66
TA = 125℃ 2 69 84
5V ≤ PVIN ≤ 14V TA = –55℃ 3 41 55
TA = 25℃ 1 53 65
TA = 125℃ 2 67 78
RDS_ON_LS Low-side switch resistance at
ILS = 6A, TPS7H4012, CFP(6)		 PVIN = 4.5V TA = –55℃ 3 30 45 mΩ
TA = 25℃ 1 40 56
TA = 125℃ 2 56 66
5V ≤ PVIN ≤ 14V TA = –55℃ 3 28 40
TA = 25℃ 1 38 50
TA = 125℃ 2 53 61
RDS_ON_HS High-side switch resistance at
IHS = 3A, TPS7H4013, HTSSOP		 PVIN = 4.5V TA = –55℃ 3 28 41 mΩ
TA = 25℃ 1 36 47
TA = 125℃ 2 46 62
5V ≤ PVIN ≤ 14V TA = –55℃ 3 26 38
TA = 25℃ 1 33 46
TA = 125℃ 2 41 56
RDS_ON_LS Low-side switch resistance at
ILS = 3A, TPS7H4013, HTSSOP		 PVIN = 4.5V TA = –55℃ 3 20 31 mΩ
TA = 25℃ 1 28 39
TA = 125℃ 2 41 50
5V ≤ PVIN ≤ 14V TA = –55℃ 3 20 29
TA = 25℃ 1 27 37
TA = 125℃ 2 39 48
RDS_ON_HS High-side switch resistance at
IHS = 3A, TPS7H4013, CFP(6)		 PVIN = 4.5V TA = –55℃ 3 42 57 mΩ
TA = 25℃ 1 54 65
TA = 125℃ 2 68 83
5V ≤ PVIN ≤ 14V TA = –55℃ 3 40 54
TA = 25℃ 1 52 64
TA = 125℃ 2 66 77
RDS_ON_LS Low-side switch resistance at
ILS = 3A, TPS7H4013, CFP(6)		 PVIN = 4.5V TA = –55℃ 3 29 44 mΩ
TA = 25℃ 1 39 55
TA = 125℃ 2 55 65
5V ≤ PVIN ≤ 14V TA = –55℃ 3 27 39
TA = 25℃ 1 37 49
TA = 125℃ 2 52 60
(1) See the 5962R21221 SMD for additional information on the QML RHA devices and see the VID for additional information on the SEP devices.
(2) Subgroups are applicable for QML parts. For subgroup definitions, see the Quality Conformance Inspection table.
(3) Use this VREF value to set the output voltage. Measured in a non-switching configuration as shown in Figure 8-1
(4) See Section 9.3.8.1.1 for additional information.
(5) The device will not begin startup until the voltage on SS discharges below SSstartup in order to ensure proper soft start functionality.
(6) Measured at pins with lead length ≈ 3mm.