AM64x/AM243x SoCs integrate PRU_ICSSG technology that enables customers to add HSR-PRP Dual Attached Node support to the system. The Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) consists of 6, 32-bit RISC cores (Programmable Real-Time Units, or PRUs), data and instruction memories, internal peripheral modules, and an interrupt controller (INTC). The programmable nature of the PRU_ICSSG, along with its access to pins, events and all SoC resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the system-on-chip (SoC).

Figure 2-1 PRU_ICSSG Functional Block Diagram.

The cores within each PRU_ICSSG have access to all resources on the SoC through the VBUSM Interface Controller port. Additionally, the external host processors can access the PRU_ICSSG resources through the VBUSP Interface Target port.

The use of XFR2VBUS allows BroadSide 32Bytes of data transfer to/from SoC CBASS0 Interconnect at 256-bit bursts using the VBUSM Controller port. The 32-bit Internal CBASS Interconnect bus will be the primary interconnect between all components internal to the PRU_ICSSG.

There are two equally symmetrical halves in each PRU_ICSSG known as SLICE0 and SLICE1. Each slice will share several resources while capable of working independently of each other. There are two sets of XFR2VBUS for each Slice. The XFR2VBUS hardware accelerator is shared between PRU0 and RTU_PRU0 for SLICE0 and the same configuration is valid for SLICE1. The TX_PRU0 and TX_PRU1 cores have also attached XFR2VBUS hardware accelerators.

The INTC handles system input events and posts events back to the device-level host CPU. The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate independently or in coordination with each other and can also work in coordination with the device-level host CPU. This interaction between processors is determined by the nature of the firmware loaded into the PRU's instruction memories.

The PRU_ICSSG also contains components such as FDB (Filter Database), XFR2PSI, and MII_G_RT (Real-time Media Independent Interface), which are key components to implementing HSR and PRP functions.

Refer AM64x/AM243x Technical Reference Manual Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) for complete details on PRU_ICSSG. For more details on PRU, please refer to the PRU Academy Training Module.