SPRACF2A April   2018  – January 2026 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359 , AM4372 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5716 , AM5718 , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM5749

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Ethernet Redundancy in Smart Grid Substations
    1. 1.1 High Availability Seamless Redundancy (HSR)
    2. 1.2 Parallel Redundancy Protocol (PRP)
  5. 2HSR/PRP Implementation in Sitara Processors
    1. 2.1 PRU_ICSSG Overview
    2. 2.2 PRU_ICSSG HSR/PRP Architecture
    3. 2.3 PRU_ICSSG HSR/PRP Features
    4. 2.4 PRU_ICSSG HSR/PRP Firmware
    5. 2.5 Benefits of PRU_ICSSG HSR/PRP
    6. 2.6 Linux HSR/PRP Solution
    7. 2.7 RTOS HSR/PRP Solution
  6. 3HSR/PRP SDK Support
  7. 4Summary
  8. 5References
  9. 6Revision History

2 HSR/PRP Implementation in Sitara Processors

The focus of this paper is to describe how the PRU_ICSSG subsystem on Texas Instruments AM64x/AM243x microprocessors implement HSR/PRP features. The following sections will start with an overview of the PRU_ICSSG subsystem and the HSR/PRP architecture, features, and firmware. At the end, a summary of the main benefits of offloading the PRU_ICSSG implementation of HSR/PRP will be given, along with how the Texas Instruments Linux and RTOS software development kits (SDKs) implement HSR/PRP.