SPRAD57 August 2022 TDA4VM
For a full architectural overview of the Jacinto devices please review the device technical reference manual of the respective SoC. Jacinto 7 SoCs target mixed criticality with a heterogenous architecture and are scalable in terms performance, peripheral, and functional safety requirements. Each device within the Jacinto family will have a slightly different partitioning of safety components as well as safety targets, this is summarized within Table 1-1.
Main Domain | MCU Domain | Extended MCU Island | Total ASIL-D/SIL-3 DMIPs | |
---|---|---|---|---|
DRA829/TDA4VM | ASIL-B/SIL-2 | ASIL-D/SIL-3 | N/A | Up to 2K |
DRA821 | ASIL-B/SIL-2 | ASIL-D/SIL-3 | ASIL-D/SIL-3 | Up to 4K |